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1. (WO2019032419) LOW-VOLTAGE CRYSTAL OSCILLATOR CIRCUIT COMPATIBLE WITH GPIO
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/032419 International Application No.: PCT/US2018/045309
Publication Date: 14.02.2019 International Filing Date: 06.08.2018
IPC:
H03B 5/36 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
B
GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
5
Generation of oscillations using amplifier with regenerative feedback from output to input
30
with frequency-determining element being electromechanical resonator
32
being a piezo-electric resonator
36
active element in amplifier being semiconductor device
Applicants:
MICROCHIP TECHNOLOGY INCORPORATED [US/US]; 2355 West Chandler Blvd. Chandler, Arizona 85224-6199, US
Inventors:
VIJAYARAGHAVAN, Rajan; US
KUMAR, Ajay; US
KARNIK, Kiran; US
Agent:
SLAYDEN, Bruce W., II; US
Priority Data:
15/987,39823.05.2018US
62/542,05007.08.2017US
Title (EN) LOW-VOLTAGE CRYSTAL OSCILLATOR CIRCUIT COMPATIBLE WITH GPIO
(FR) CIRCUIT OSCILLATEUR À QUARTZ BASSE TENSION COMPATIBLE AVEC UN GPIO
Abstract:
(EN) Low voltage crystal oscillator having native NMOS transistors used for coupling/decoupling to/from GPIO. The native NMOS transistors function properly at a low supply voltage when on (low resistance) and a high supply voltage when off (high resistance). Oscillator Gm driver bias resistors are repurposed to degenerate the native NMOS transistors when they are off, thereby reducing the leakage current thereof (oscillator circuit decoupled from GPIO nodes). This ensures compliance with the CMOS IIH leakage current specification during an external clock (EC) mode at a high supply voltage.
(FR) La présente invention concerne un oscillateur à quartz basse tension, comprenant des transistors NMOS natifs servant au couplage à un GPIO ou au découplage de ce dernier. Les transistors NMOS natifs fonctionnent correctement à une faible tension d'alimentation quand ils sont sous tension (faible résistance) et à une tension d'alimentation élevée quand ils sont hors tension (résistance élevée). Des résistances de polarisation de pilote Gm d'oscillateur sont transformées de façon à dégénérer les transistors NMOS natifs quand ces derniers sont hors tension, ce qui permet de réduire le courant de fuite correspondant (circuit oscillateur découplé des nœuds GPIO). Ceci garantit le respect de la spécification de courant de fuite IIH CMOS pendant un mode d'horloge externe (EC) à une tension d'alimentation élevée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)