Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019032322) MOLDED CHIP COMBINATION
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/032322 International Application No.: PCT/US2018/044342
Publication Date: 14.02.2019 International Filing Date: 30.07.2018
IPC:
H01L 25/065 (2006.01) ,H01L 23/31 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
ADVANCED MICRO DEVICES, INC. [US/US]; 2485 Augustine Drive Santa Clara, CA 95054, US
Inventors:
BHAGAVAT, Milind S.; US
FU, Lei; US
BARBER, Ivor; US
LEONG, Chia-Ken; US
AGARWAL, Rahul; US
Agent:
HONEYCUTT, Timothy Mark; US
Priority Data:
15/675,21411.08.2017US
Title (EN) MOLDED CHIP COMBINATION
(FR) COMBINAISON DE PUCES MOULÉE
Abstract:
(EN) Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip (20) that has a first PHY region (75), a second semiconductor chip (19) that has a second PHY region (65), an interconnect chip (85) interconnecting the first PHY region to the second PHY region, and a molding (25) joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.
(FR) La présente invention concerne diverses combinaisons de puces moulées et leurs procédés de fabrication. Selon un aspect, l'invention porte sur une combinaison de puces moulée qui comprend une première puce de semi-conducteur (20) qui comporte une première région PHY (75), une seconde puce de semi-conducteur (19) qui comporte une seconde région PHY (65), une puce d'interconnexion (85) interconnectant la première région PHY à la seconde région PHY, et un moulage (25) réunissant ensemble la première puce de semi-conducteur, la seconde puce de semi-conducteur et la puce d'interconnexion.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)