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1. (WO2019032313) METHOD OF MANUFACTURING AN ELECTRONICS USING DEVICE-LAST OFR DEVICE-ALMOST LAST PLACEMENT
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/032313 International Application No.: PCT/US2018/044101
Publication Date: 14.02.2019 International Filing Date: 27.07.2018
IPC:
H01L 23/13 (2006.01) ,H01L 23/14 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/48 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
KAPUSTA, Christopher, James; US
FILLION, Raymond, Albert; US
TUOMINEN, Risto Ilkka, Sakari; JP
NAGARKAR, Kaustubh, Ravindra; US
Agent:
DIMAURO, Peter, T.; US
KRAMER, John, A.; US
ZHANG, Douglas, D.; US
WINTER, Catherine, J.; US
MIDGLEY, Stephen, G.; US
Priority Data:
15/670,42307.08.2017US
Title (EN) METHOD OF MANUFACTURING AN ELECTRONICS USING DEVICE-LAST OFR DEVICE-ALMOST LAST PLACEMENT
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF ÉLECTRONIQUE UTILISANT UN PLACEMENT DE DERNIER DISPOSITIF POUR PRESQUE DERNIER DISPOSITIF
Abstract:
(EN) A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.
(FR) Un procédé de fabrication selon l'invention d'un boîtier électronique multicouche comprend la fixation d'un substrat isolant de base à un cadre ayant une ouverture de telle sorte que le cadre est positionné au-dessus et/ou au-dessous du substrat isolant de base pour servir de support à celui-ci. Une première couche de câblage conductrice est appliquée sur le premier côté du substrat isolant de base, et des trous d'interconnexion sont formés dans le substrat isolant de base. Une seconde couche de câblage conductrice est formée sur le second côté du substrat isolant de base qui recouvre les trous d'interconnexion et les parties exposées de la première couche de câblage conductrice, et au moins un substrat isolant supplémentaire est lié au substrat isolant de base. Des trous d'interconnexion sont formés dans chaque substrat isolant supplémentaire et une couche de câblage conductrice supplémentaire est formée sur chaque substrat isolant supplémentaire. L'accumulation décrite forme une structure d'interconnexion multicouche, le cadre fournissant un support pour cette accumulation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)