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1. (WO2019032271) MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE
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CLAIMS

What is claimed is:

J 1. An electronic memory apparatus, comprising:

an array of memory ceils;

3 a controller configured to control access to the array of memory cells;

an interposer to operatively couple the array of memory cells with the

5 controller, the interposer including a plurality of channels between the array of memory cells

6 and the controller, and

7 a receiver configured to decode a multi-level signal modulated using a first

8 modulation scheme having at least three levels communicated across at least one channel of

9 the interposer.

1 2. The apparatus of claim 1, further comprising:

a driver configured to generate the multi-level signal to be transmitted across

3 the at least one channel of the interposer based at least in part on a plurality of information bits.

1 3. The apparatus of claim 1, wherein the receiver further comprises:

2 a plurality of comparators, each comparator configured to compare the multi- 3 level signal to a voltage threshold.

1 4. The apparatus of claim 3, wherein the receiver further comprises:

a decoder configured to determine a plurality of bits represented by the multi - 3 level signal based at least in part on information received from a set of the plurality of

comparators.

5. The apparatus of claim 1, wherein:

a plurality of information bits are represented by an amplitude of the multi - level signal.

1 6. The apparatus of claim 1, wherein:

the multi-level signal is encoded with information using a pulse-amplitude

3 modulation (PAM) scheme.

7. The apparatus of claim 1, wherein:

the controller transmits the multi-level signal across a subset of the plurality of channels of the interposer to the array of memory cells.

8. The apparatus of claim 1, wherein:

the controller transmits the multi-level signal using a unidirectional channel of the interposer.

9. The apparatus of claim 1, wherein:

the array of memory cells transmits the multi-level signal across a subset of the plurality of channels of the interposer to the controller.

10. The apparatus of claim 1, further comprising:

a substrate formed of a first material, wherein the interposer is formed of a second material different from the first material .

11. The apparatus of claim 10, wherein:

the second material comprises silicon.

12. The apparatus of claim 1 , further comprising:

a second array of mem or ' cells stacked on top of the array of memory cells, wherein the second array of memory cells is operatively coupled with the controller by the interposer.

13. The apparatus of claim 1, further comprising:

an input/output device coupled with the array of memory cells and the interposer, wherein the input/output device is configured to buffer information communicated with the array of memory cells.

14. The apparatus of claim 1, further comprising:

a driver configured to encode data using gray coding or data bus inversion or both.

J 5. A method, compri sing :

identifying, by a controller of a memory device, information to be written to an array of memory cells;

generating, by the controller, a multi -lev el signal modulated using a first

5 modulation scheme having at least three levels that represent a plurality of bits of the

6 identified information, and

7 transmitting, by the controller, the multi-level signal to the array of memory

8 cells across an interposer that includes a plurality of channels,

1 16. The method of claim 15, further comprising:

determining, by the array of memory cells, whether an amplitude of the multi- 3 level signal satisfies one or more thresholds.

J 17. The method of claim 16, further comprising:

identifying, by the array of memory cells, the plurality of bits represented by

3 the multi-level signal based at least in part on a number of thresholds of the one or more thresholds that are satisfied by the multi-level signal.

1 18. The method of claim 17, further comprising:

writing, by the array of memory cells, the plurality of bits represented by the

3 multi -lev el signal to one or more memory cells of the array of memory cells.

J 19. The method of claim 15, further comprising:

transmitting, by the controller, a binary-level signal to the array of memory

3 cells across the interposer simultaneously with the multi-level signal.

1 20. An electronic memory apparatus, comprising:

an array of memory ceils;

3 an interposer operatively coupled with the array of memory ceils, the

interposer that includes a plurality of channels;

5 a controller operatively coupled with the interposer, the controller configured

6 to:

7 identify information to be written to the array of memory cells;

8 generate a multi-level signal modulated using a first modulation

9 scheme having at least three levels that represent a plurality of bits of the identified 0 information; and

1 transmit the multi-level signal to the array of memory cells across the interposer.

21. An electronic memory apparatus, comprising:

means for identifying information to be written to an array of memory cells; means for generating a multi-level signal modulated using a first modulation scheme having at least three levels that represent a plurality of bits of the identified information; and

means for transmitting the multi-level signal to the array of memory cells across an interposer that includes a plurality of channels.