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1. (WO2019032211) ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/032211 International Application No.: PCT/US2018/039464
Publication Date: 14.02.2019 International Filing Date: 26.06.2018
IPC:
H01L 23/485 (2006.01) ,H01L 23/498 (2006.01) ,H01L 23/528 (2006.01) ,H01L 23/14 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
KAPUSTA, Christopher, James; US
NAGARKAR, Kaustubh, Ravindra; US
GOWDA, Arun, Virupaksha; US
ROSE, James, Wilson; US
Agent:
DIMAURO, Peter, T.; US
WINTER, Catherine, J.; US
MIDGLEY, Stephen, G.; US
KRAMER, John, A.; US
ZHANG, Douglas, D.; US
Priority Data:
15/675,14411.08.2017US
Title (EN) ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME
(FR) BOÎTIER ÉLECTRONIQUE COMPORTANT UN ENSEMBLE D'INTERCONNEXION À ALIGNEMENT AUTOMATIQUE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.
(FR) L'invention concerne un boîtier électronique comprenant un ensemble d'interconnexion comprenant un premier substrat isolant, une première couche de câblage formée sur une surface inférieure du premier substrat isolant, et au moins un trou traversant s'étendant à travers le premier substrat isolant et la première couche de câblage. Le boîtier électronique comprend également un ensemble composant électrique comprenant un composant électrique ayant une surface active couplée à une surface supérieure du premier substrat isolant opposée à la surface inférieure. La surface active de l'appareil électrique comprend au moins un plot de contact métallique. Au moins un plot conducteur est couplé à l'au moins un plot de contact métallique et est positionné à l'intérieur de l'au moins un trou traversant. Une fiche conductrice entre en contact avec la première couche de câblage et s'étend dans l'au moins un trou traversant pour entourer au moins partiellement l'au moins un plot conducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)