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1. (WO2019032166) TWO-DIMENSIONAL ARRAY OF SURROUND GATE VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/032166 International Application No.: PCT/US2018/033899
Publication Date: 14.02.2019 International Filing Date: 22.05.2018
IPC:
H01L 27/088 (2006.01) ,H01L 27/24 (2006.01) ,H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; 5080 Spectrum Drive Suite 1050W Addison, Texas 75001, US
Inventors:
SEL, Jongsun; US
OTOI, Hisakazu; US
TAKAKI, Seje; US
PHAM, Tuan; US
Agent:
RADOMSKY, Leon; US
COHN, Joanna; US
CONNOR, David; US
GAYOSO, Tony; US
GEMMELL, Elizabeth; US
GILL, Matthew; US
GREGORY, Shaun; US
GUNNELS, Zarema; US
HANSEN, Robert; US
HUANG, Stephen; US
HYAMS, David; US
JOHNSON, Timothy; US
MAZAHERY, Benjamin; US
MURPHY, Timothy; US
NGUYEN, Jacqueline; US
O'BRIEN, Michelle; US
PARK, Byeongju; US
RUTT, Steven; US
SIMON, Phyllis; US
SMITH, Jackson; US
SULSKY, Martin; US
Priority Data:
15/672,92909.08.2017US
Title (EN) TWO-DIMENSIONAL ARRAY OF SURROUND GATE VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF
(FR) RÉSEAU BIDIMENSIONNEL DE TRANSISTORS À EFFET DE CHAMP VERTICAL À GRILLE CIRCULAIRE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) The disclosed two-dimensional array of vertical field effect transistors (200A) includes a one-dimensional array of ladder-shaped gate electrode lines (52), each including a pair of rail portions (522) that extend laterally along a first horizontal direction (hd1) and are spaced along a second horizontal direction (hd2), and rung portions (524) extending between the rail portions along the second horizontal direction. Each vertical field effect transistor includes a gate dielectric (50) located in an opening defined by a neighboring pair of rung portions, and a vertical semiconductor channel (14) laterally surrounded by the gate dielectric. The two-dimensional array of vertical field effect transistors can be employed to select vertical bit lines (90) of a three-dimensional ReRAM device (300).
(FR) L'invention concerne un réseau bidimensionnel de transistors à effet de champ vertical (200A) comprenant un réseau unidimensionnel de lignes d'électrode de grille en forme d'échelle (52), comprenant chacune une paire de parties de rail (522) qui s'étendent latéralement le long d'une première direction horizontale (hd1) et qui sont espacées le long d'une seconde direction horizontale (hd2), et des parties en échelon (524) s'étendant entre les parties de rail le long de la seconde direction horizontale. Chaque transistor à effet de champ vertical comprend un diélectrique de grille (50) situé dans une ouverture définie par une paire voisine de parties en échelon, et un canal semi-conducteur vertical (14) entouré latéralement par le diélectrique de grille. Le réseau bidimensionnel de transistors à effet de champ vertical peut être utilisé pour sélectionner des lignes de bits verticales (90) d'un dispositif ReRAM tridimensionnel (300).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)