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1. (WO2019032115) QUBIT DEVICES WITH JOSEPHSON JUNCTIONS CONNECTED BELOW SUPPORTING CIRCUITRY
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QUBIT DEVICES WITH JOSEPHSON JUNCTIONS CONNECTED BELOW SUPPORTING CIRCUITRY

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to Josephson Junctions for use in quantum circuits and to methods of fabricating thereof.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. These quantum-mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

[0003] Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states - a uniquely quantum-mechanical phenomenon. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.

[0004] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results.

Brief Description of the Drawings

[0005] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0006] FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit, according to some embodiments of the present disclosure.

[0007] FIGS. 2A-2C provide a schematic illustration of a photoresist mask provided over a substrate for fabricating a Josephson Junction using a double-angle shadow evaporation approach.

[0008] FIGS. 3A-3C provide a schematic illustration of fabricating Josephson Junctions using a conventional double-angle shadow evaporation approach.

[0009] FIG. 4 provides a flow chart of a superconductor (SC) bilayer stack method for fabricating quantum circuit assemblies with Josephson Junctions connected below the plane of supporting circuitry, according to some embodiments of the present disclosure.

[0010] FIGS. 5A-5H are cross-sections illustrating various exemplary stages in the manufacture of a first embodiment of a quantum circuit assembly using the SC bilayer stack method of FIG. 2, in accordance with various embodiments of the present disclosure.

[0011] FIGS. 6A-6B are cross-sections illustrating various exemplary stages in the manufacture of a second embodiment of a quantum circuit assembly using the SC bilayer stack method of FIG. 2, in accordance with various embodiments of the present disclosure.

[0012] FIGS. 7A and 7B are top views of a wafer and dies that may include one or more of quantum circuit assemblies disclosed herein.

[0013] FIG. 8 is a cross-sectional side view of a device assembly that may include one or more of quantum circuit assemblies disclosed herein.

[0014] FIG. 9 is a block diagram of an exemplary quantum computing device that may include one or more of quantum circuit assemblies disclosed herein, in accordance with various embodiments.

Detailed Description

Overview

[0015] As briefly described above, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0016] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Therefore, both the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits.

[0017] Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, single trapped ion qubits, Silicon (Si) quantum dot qubits, photon polarization qubits, etc.

[0018] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction.

[0019] Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits. In general, a Josephson Junction includes two superconductors coupled by a so-called weak link that weakens the superconductivity between the two superconductors. In quantum circuits, the weak links of Josephson Junctions have conventionally been implemented by providing a thin layer of an insulating material, typically referred to as a "barrier" or a "tunnel barrier," sandwiched, in a stack-like arrangement, between two layers of superconductor, which two superconductors typically referred to, respectively, as a "bottom/base electrode" and a "top electrode" of a Josephson Junction.

[0020] Another type of integral building blocks in superconducting quantum circuits are resonators used to couple qubits together and to set qubit frequencies. In general, a resonator of a quantum circuit is a microwave transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions (i.e. a resonant microwave transmission line).

[0021] A method conventionally used to fabricate Josephson Junctions is known as a "double-angle shadow evaporation" method (also sometimes referred to as "double-angle shadow evaporation" or "hanging resist" method). The name "double-angle shadow evaporation/evaporation" reflects the

fact that the method involves metal deposition, typically carried out by metal evaporation, at two different angles of incidence with respect to the substrate (hence, double-angle). The name further reflects the fact that metal deposition is performed through a hanging photoresist mask which casts a shadow on at least a part of the substrate, obscuring metal deposition on that part (hence, shadow evaporation/evaporation). Once a Josephson Junction is formed, an ex-situ process is typically applied to form supporting circuitry for the Josephson Junction and to connect the Josephson Junction to other circuit elements, such as e.g. resonators, shunt capacitors, and various non-resonant transmission lines typically present in a quantum circuit.

[0022] One drawback with such conventional implementations is that oftentimes electrodes of Josephson Junctions are made out of a superconductor different from that used for making the supporting circuitry and, in particular, the electrically conductive connections to the Josephson Junctions. For example, Josephson Junction electrodes are often made out of aluminum because aluminum can be easily deposited and oxidized to create a tunnel barrier of a Josephson Junction, while connections to Josephson Junctions are often made of superconductors such as e.g. niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors because it is easier to fabricate high quality factor resonators from superconducting metals other than aluminum. The problem with this is that the ex-situ process can make the connection between two dissimilar superconductors problematic due to surface oxide that develops on the superconductor that is deposited first. Therefore, making a robust electrical connection can be a challenge. This may be addressed with an in-situ etch or sputter processes which remove the oxide just prior to the deposition of the second superconductor, but such processes are thought to introduce detrimental effects, e.g. increase amount of spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be the dominant source of superconducting qubit decoherence. Therefore, improvements with respect to providing connections to Josephson Junctions for use in quantum circuits employing superconducting qubits are desirable.

[0023] Embodiments of the present disclosure propose methods of fabricating quantum circuit assemblies that include Josephson Junctions, as well as qubit devices comprising Josephson Junctions, that could improve on one or more of the drawbacks described above. In one aspect of the present disclosure, a method of fabricating a quantum circuit assembly with at least one Josephson Junction is disclosed. The disclosed method is based on providing a first conductive layer over a substrate and a second conductive layer over the first conductive layer, thus forming a bilayer stack of conductive materials over a substrate and giving rise to the name "bilayer stack method" used herein to describe this method. The bilayer stack method further includes patterning the

second conductive layer to define first and second conductive circuit elements out of the material of the second conductive layer, and then patterning a portion of the first conductive layer that was exposed by patterning the second conductive layer to form a first lead electrically connected to the second conductive layer of the first conductive circuit element and a second lead electrically connected to the second conductive layer of the second conductive circuit element, the first and second leads being formed out of the material of the first conductive layer. The first conductive layer is also patterned so that each of the first and second conductive circuit elements has an upper portion made of the material of the second conductive layer and a lower portion made of the material of the first conductive layer. The bilayer stack method also includes forming a Josephson Junction that will be connected to the first and second leads.

[0024] The first and second conductive circuit elements are examples of supporting circuitry for a quantum circuit assembly, in particular examples of supporting circuitry that is electrically connected to a Josephson Junction of a superconducting qubit. In general, a distinction can be made between supporting circuitry elements which are electrically connected to one or more Josephson Junctions of a superconducting qubit, such as e.g. shunt capacitors, superconducting loops of a

superconducting quantum interference device (SQUID), etc., referred to herein as "qubit supporting circuitry," and supporting circuitry elements which are capacitively or magnetically coupled to a qubit but are not directly electrically connected to Josephson Junctions, such as e.g. resonators, flux bias lines, microwave feed lines, etc., referred to herein as "chip supporting circuitry." In some embodiments, the bilayer stack method described herein may also be used to form conductive circuit elements of at least some elements of chip supporting circuitry, e.g. conductive circuit elements of resonators, flux bias lines, microwave feed lines, etc., in a manner similar to that described for the qubit supporting circuitry in the form of the first and second conductive circuit elements described herein. In other embodiments, some or all of the chip supporting circuitry may be formed by a conventional single layer process.

[0025] As the foregoing summary of the bilayer stack method illustrates, the leads to the future Josephson Junction are formed out of the bottom layer material of the bilayer stack (e.g. Al), while exemplary supporting circuitry in the form of the first and second conductive circuit elements is formed out of both the top layer material of the bilayer stack (e.g. Nb, NbN, TiN, or NbTiN) and the bottom layer material of the bilayer stack (e.g. Al). Because the bilayer stack is formed in an in-situ process prior to forming a Josephson Junction, the interface between two dissimilar conductive materials of the bilayer stack may be significantly improved in that no, or substantially less, uncontrolled oxide will be formed on the conductive material that is deposited first, compared to conventional implementations described above. Furthermore, in some implementations, using two

dissimilar conductive materials with different etch properties (i.e. using the materials which are etch-selective with respect to one another) for the first and second layers of the bilayer stack may provide a particularly easy manner to form supporting circuitry for a Josephson Junction out of the material of the second (top) layer while forming the leads for the Josephson Junction out of the material of the first (bottom) layer of the bilayer stack. However, in other implementations, the bilayer stack method described herein can also use the same conductive material for the first and second conductive layers of the bilayer stack, where, rather than relying on different etch selectivity, a timed etch is used to separate formation of the supporting circuitry and formation of the leads for a Josephson Junction. In such implementations, the name "bilayer stack" is still appropriate in that it implies that different layers of a layer of a single conductive material are used for forming leads for Josephson Junctions and supporting circuitry.

[0026] Using the bilayer stack method as described herein allows forming a quantum circuit assembly with qubit devices (e.g. superconducting qubit devices such as e.g. transmons), or, more generally, with quantum circuit components, which include Josephson Junction(s) having leads connected below the plane of the supporting circuitry, where, as used herein, "connected below the plane of supporting circuitry" is used to describe connections at/to the lower portions (e.g. bottom sides) of the supporting circuitry. For example, in one aspect of the present disclosure, a quantum circuit assembly includes supporting circuitry in the form of a first and a second conductive circuit elements provided over a substrate, each circuit element having an upper portion and a lower portion. Such a quantum circuit assembly further includes a Josephson Junction provided over the substrate and electrically connected to the first and second conductive circuit elements via a first lead and a second lead, where the first lead electrically connects a first electrode of the Josephson Junction to the lower portion of the first conductive circuit element, and the second lead electrically connects a second electrode of the Josephson Junction to the lower portion of the second conductive circuit element. In embodiments where a Josephson Junction is oriented vertically (i.e. the stack of superconductor-insulator-superconductor is oriented vertically), the first and second electrodes of a Josephson Junction could be, respectively, bottom and top electrodes. In other embodiments, a Josephson Junction could be oriented horizontally.

[0027] In one embodiment of the bilayer stack method, a Josephson Junction may be formed over the first lead described herein. In another embodiment, a Josephson Junction may be formed between the first and second leads. In the former embodiment, a Josephson Junction may be formed by providing a layer of oxide over at least a portion of the first lead, and depositing a strip of conductive material over a portion of the second lead and over the layer of oxide provided over the portion of the first lead. In such an embodiment, a portion of the first lead may form the bottom

electrode of a Josephson Junction, the layer of oxide provided over the first lead may form the tunnel barrier of the Josephson Junction, and a portion of the strip of conductive material provided over a portion of the second lead and over the oxide may form the top electrode of the Josephson Junction. In the latter embodiment, a Josephson Junction may be formed between the first and second leads using double-angle shadow evaporation as otherwise known in the art.

[0028] In order to provide substantially lossless connectivity to, from, and between the qubits, electrically conductive portions of various quantum circuit elements described herein (e.g. first and second conductive circuit elements, first and second leads, bottom and top electrodes of Josephson Junctions, first and second conductive layers of a bilayer stack, or a strip of conductive material provided to form the top electrode of a Josephson Junction) may be made from one or more superconductive materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconductive. In the following, unless specified otherwise, reference to an electrically conductive material or circuit element implies that a superconductive material can be used and vice versa (i.e. reference to a superconductor implies that a conductive material which is not superconductive may be used). Furthermore, materials described herein as "superconductive/superconducting materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions, e.g.

materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate, but which may not exhibit such behavior at e.g. room temperatures.

[0029] While some descriptions are provided with reference to superconducting qubits, in particular to transmons, a particular class of superconducting qubits, at least some teachings of the present disclosure may be applicable to implementations of any qubits, including superconducting qubits other than transmons and/or including qubits other than superconducting qubits, which may employ Josephson Junctions, all of which implementations are within the scope of the present disclosure. For example, the bilayer stack method and the resulting qubit devices described herein may be used in hybrid semiconducting-superconducting quantum circuits.

[0030] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0031] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order

dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0032] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0033] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0034] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.

Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious TLS's may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0035] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are typically operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GHz, e.g. in 5-10 GHz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.

Quantum computing and Joseohson Junctions

[0036] FIG. 1 provides a schematic illustration of an exemplary superconducting quantum circuit 100 that may include any of the quantum circuit assemblies described herein.

[0037] As shown in FIG. 1, an exemplary superconducting quantum circuit 100 may include two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element). Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 electrically connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit. The circuit elements 106 could be e.g. shunt capacitors, superconducting loops of a SQUI D, electrodes for setting an overall capacitance of a qubit, or/and ports for capacitively coupling the qubit to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line or electromagnetically coupling the qubit to a flux bias line.

[0038] In general, a SQUID includes a pair of Josephson Junctions and a loop of a conductive, typically superconductive material (i.e. a superconducting loop), connecting the pair of Josephson Junctions. Applying magnetic field to the SQUI D region of a superconducting qubit allows controlling a frequency of the qubit which, in turn, allows controlling whether the qubit interacts with other components of a quantum circuit, e.g. with other qubits. Applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive line generally referred to as a "flux bias line" (also known as a "flux line" or a "flux coil line"). By providing flux bias lines sufficiently close to SQUI Ds, magnetic fields generated as a result of currents running through the flux bias lines extend to the SQUIDs, thus tuning qubit frequencies.

[0039] Microwave drive lines (also known as "microwave lines" or "drive lines") are typically used to control the state of the qubits by providing a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.

[0040] As also shown in FIG. 1, an exemplary quantum circuit 100 typically includes a plurality of non-resonant transmission lines 108 and a plurality of resonators 110, e.g. coupling and readout resonators.

[0041] The non-resonant transmission lines 108 are typically used for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits. For example, for superconducting qubits, examples of the non-resonant transmission lines 108 include flux bias lines, microwave feed lines, and direct drive lines.

[0042] In general, a resonator 110 of a quantum circuit differs from a non-resonant microwave transmission line 108 in that a resonator is a transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions. In contrast, non-resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonators in the proximity of such non-resonant lines. Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible. For example, the ends of non-resonant transmission lines are typically engineered to have a specific impedance (e.g. substantially 50 Ohm) to minimize impedance mismatches to other circuit elements to which the lines are connected, in order to minimize the amount of reflected signal at transitions (e.g., transitions from the chip to the package, the package to the connector, etc.).

[0043] A resonator is made with fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line structure used to implement a resonator. In order to satisfy boundary conditions for resonance, each end of a transmission line that implements a resonator can be either a node, if it is shorted to ground (e.g. by being electrically connected to a ground plane of a transmission line structure that implements the resonator, or to any other ground potential), or an antinode, if it is capacitively or inductively coupled to another quantum circuit element. Thus, resonators 110 differ from non-resonant microwave transmission lines 108 in how these lines are terminated. A line used to route a signal on a substrate, i.e. one of the non-resonant transmission lines 108, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to a quantum dot device or another bonding pad or another electrical connection to a load). In other words, non-resonant transmission lines 108 terminate with direct electrical connections to sources and loads. On the other hand, a transmission line resonator is typically composed of a piece of transmission line terminated with an open or short circuit. In this case, for a desired resonant frequency, transmission line length may e.g. be a multiple of a microwave wavelength divided by 4. However, other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above. For example, capacitive terminations may be used for resonators which are coupled to a line or another resonator by capacitors.

[0044] Besides line termination by capacitive or inductive coupling or a short circuit, in order to support resonant oscillations, transmission lines of the resonators 110 need to be of a specific length that can support such oscillations. That is why, often times, resonators 110 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).

[0045] One type of the resonators 110 used with superconducting qubits are so-called coupling resonators (also known as "bus resonators"), which allow coupling different qubits together in order to realize quantum logic gates. A coupling resonator may be implemented as a microwave transmission line that includes capacitive or inductive connections to ground on both sides (e.g. a half wavelength resonator), which results in oscillations (resonance) within the transmission line. While the ends of a coupling resonator have open circuits to the ground, each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in sufficient proximity to the qubit. Because each side of a coupling resonator has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit, a necessary functionality for implementing logic gates.

[0046] Another type of the resonators 110 used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits. In some embodiments, a corresponding readout resonator may be provided for each qubit. A readout resonator is similar to a coupling resonator in that it may be implemented as a transmission line that includes a capacitive or an inductive connection to ground on one side. On the other side, a readout resonator may either have a capacitive connection to ground (for a half wavelength resonator) or may have a short circuit to the ground (for a quarter wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. A readout resonator is coupled to a qubit by being in sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.

[0047] The circuit elements 106, the non-resonant transmission lines 108, and the resonators 110 may be considered, broadly, as "supporting circuitry" for the superconducting qubits 102 or/and the Josephson Junctions 104, where, as described above, a further distinction could be made between "qubit supporting circuitry" in the form of the circuit elements 106 and "chip supporting circuitry" in the form of the non-resonant transmission lines 108 and the resonators 110. Further, any other connections for providing microwave or other electrical signals to different circuit elements and components of the quantum circuit 100, such as e.g. connections between electrodes of various circuit components, or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, may be considered as being within the general category of "supporting circuitry." Still further, the term "supporting circuitry" may also be used to refer to elements providing electrical interconnections to/from/between quantum circuit elements/components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog-to-digital converters, mixers, multiplexers, amplifiers, etc.

[0048] At least some of the Josephson Junctions 104 shown in FIG. 1 may be implemented by being connected, via their respective leads, below (i.e. to the lower portions of) at least some conductive circuit elements of such qubit supporting circuitry, as described herein.

[0049] In various embodiments, various conductive circuit elements of supporting circuitry included in a quantum circuit such as the quantum circuit 100 could have different shapes and layouts. In general, the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so. For example, some resonant or non-resonant transmission lines or parts thereof (e.g. conductor strips of resonant or non-resonant transmission lines) may comprise more curves, wiggles, and turns while other resonant or non-resonant transmission lines or parts thereof may comprise less curves, wiggles, and turns, and some transmission lines or parts thereof may comprise substantially straight lines.

[0050] In some embodiments, materials forming various conductive circuit elements of supporting circuitry, and in particular the resonator structures described herein, may include niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and/or niobium titanium nitride (NbTiN), all of which are particular types of superconductors at qubit operating temperatures, as well as their alloys. However, in various embodiments, other suitable superconductors as well as non-superconducting conductors may be used as well, all of which may be referred to "conductive" or "electrically conductive" materials.

[0051] The qubits 102, the non-resonant transmission lines 108, and the resonators 110 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1).

[0052] In various embodiments, quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a quantum system. Joseo son Junctions connected below supporting circuitry

[0053] In order to highlight the advantages offered by novel quantum circuit assemblies fabricated using the bilayer stack method proposed herein, it would be helpful to first explain how Josephson Junctions are fabricated using the double-angle shadow evaporation in conventional quantum circuits.

[0054] FIGS. 2A-2C provide a schematic illustration of one example of a photoresist mask 200 provided over a substrate 202 for fabricating Josephson Junctions using a double-angle shadow evaporation approach. Each of FIGS. 2A-2C provides a view of the same photoresist mask 200 over the substrate 202, but perspectives of these views are different. FIG. 2A provides a top down view (i.e. a view from a point above the substrate 202). FIG. 2B provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a horizontal dashed line shown in FIG. 2A. Finally, FIG. 2C provides a cross-sectional view with a cross-section of the structure of FIG. 2A taken along a vertical dashed line shown in FIG. 2A. A legend provided within a dashed box at the bottom of FIGS. 2A-2C illustrates patterns used to indicate different elements shown in FIGS. 2A-2C, so that the FIGs are not cluttered by many reference numerals.

[0055] Josephson Junctions may be created by a double-angle shadow evaporation approach using a two-layer photoresist mask 200 that includes a bottom photoresist layer 204 and a top photoresist layer 206 as shown in FIGS. 2A-2C. The bottom layer 206 is undercut from the top layer 204 in that some portions of the top layer 204 hang, or are suspended, over the bottom layer 206. The bottom layer 206 is undercut in such a manner that the top layer 204 of photoresist forms a suspended bridge 208, known as a Dolan bridge, over a section of the substrate 202. Ways for fabricating such undercuts in photoresist are well known in the art of photolithographic processing and, therefore, are not described here in detail.

[0056] In order to form a Josephson Junction, metals are then deposited through the photoresist mask 200 with the suspended bridge. Conventionally, this is done as illustrated in FIGS. 3A-3C.

[0057] Each of FIGS. 3A-3C illustrates a result of different subsequent fabrication steps. FIG. 3C provides two views of the same structure. The view on the right side of FIG. 3C is a top down view (i.e. a view similar to that shown in FIG. 2A). The view on the left side of FIG. 3C is a cross-sectional view with a cross-section of the structure of FIG. 3C taken along a horizontal dashed line shown in FIG. 3C (i.e. a view similar to that shown in FIG. 2B). Each of FIGS. 3A and 3B only provide a cross-sectional view similar to that of the left side of FIG. 3C but at an earlier fabrication step. Similar to FIGS. 2A-2C, a legend provided within a dashed box at the bottom of FIGS. 3A-3C illustrates patterns used in the figures to indicate different elements shown in FIGS. 3A-3C. Moreover, similar reference numerals in FIGS. 2A-2C and FIGS. 3A-3C are used to illustrate analogous elements in the figures. For example, reference numerals 202 and 302, shown, respectively, in FIGS. 2 and 3 refer to a substrate, reference numerals 204 and 304 - to a bottom mask layer, and so on. When provided with reference to one of the FIGS. 2A-2C and FIGS. 3A-3C, discussions of these elements are applicable to other figures, unless stated otherwise. Thus, in the interests of brevity, discussions of similar elements are not repeated for each of the figures but, rather, the differences between the figures are described.

[0058] As previously described herein, a Josephson Junction comprises a thin layer of dielectric sandwiched between two layers of superconductors, the dielectric layer acting as the barrier in a superconducting tunnel junction. According to the double-angle shadow evaporation approach, such a device is conventionally fabricated by, first, depositing a layer of a first superconductor 310 on the substrate 302, as shown in FIG. 3A, through the two-layer mask such as e.g. the one shown in FIGS. 2A-2C. The first superconductor is deposited at an angle with respect to the substrate 302, as shown in FIG. 3A with an angle Θ1. Slanted dotted-dashed lines in FIG. 3A illustrate the direction of deposition of the first superconductor 310. A layer of the first superconductor 310 may have a thickness between e.g. about 10 and 200 nanometers (nm), e.g. between about 30 and 100 nm.

[0059] The first superconductor 310 forms a bottom (base) electrode of the future Josephson Junction. A layer of insulator 311 (also referred to herein as a "dielectric layer 311" or a "dielectric 311"), shown in FIGs. 3B and 3C, is then provided over the first superconductor 310 to form a tunnel barrier of the future Josephson Junction. The tunnel barrier is formed by oxidizing the first superconductor 310, thus creating a layer of first superconductor oxide on its surface. Such an oxide may have a thickness between e.g. about 1 and 5 nm, typically for qubit applications between about 1 and 2 nm.

[0060] The fact that the choice of a tunnel barrier in a double-angle shadow evaporation method is constrained to an oxide of the base electrode superconductor limits the choice of the

superconductor used as the first superconductor 310 in that the superconductor must be such that a controlled layer of oxide may be created on it. In practice, aluminum oxide is the only controlled oxide that may be formed from a metal. Therefore, currently aluminum is the only superconducting metal that is used for the base electrode of Josephson Junctions fabricated using the double-angle shadow evaporation technique.

[0061] After the layer of dielectric 311 is provided on the first superconductor 310, a second superconductor 312 is deposited through the mask but at a different angle with respect to the substrate 302 than Θ1. FIG. 3B illustrates the second angle as an angle Θ2 and slanted dotted-dashed lines in FIG. 3B illustrate the direction of deposition of the second superconductor 312. In some embodiments, the first and the second superconductors 310, 312 are deposited at the opposite angles, if measured with respect to a normal to the substrate 302. Conventionally, the second superconductor 320 is aluminum because the first superconductor must be aluminum, as described above. A layer of the second superconductor 312 may have a thickness between e.g. about 10 and 200 nm, typically between about 30 and 100 nm. The second superconductor 312 forms a counter electrode (i.e. counter to the bottom electrode formed by the first superconductor 310) of the future Josephson Junction, typically referred to as a "top" electrode.

[0062] The first and second superconductors 310, 312 are usually deposited using a non-conformal process, such as e.g. evaporative deposition. After deposition of the second superconductor 312, the deposition mask is removed, removing with it any first and/or second superconductor 310, 312 deposited on top of it.

[0063] In general, the above-described process of creating patterned structures of one or more target materials (in this case, structures made of the first and second superconductors 310, 312) on the surface of a substrate using a sacrificial material such as photoresist is referred to as a lift-off method. Lift-off is a type of an additive technique, as opposed to subtracting techniques like etching, and may be applied in cases where a direct etching of structural material would have undesirable effects on one or more layers below.

[0064] After the deposition mask is removed, the resulting Josephson Junction is left on the substrate 302 as shown in FIG. 3C as a Josephson Junction 314. The Josephson Junction 314 is formed by the small region of overlap under the photoresist bridge 308 (i.e. the area under the bridge 308 where the first superconductor 310, covered with a layer of a thin insulating material is overlapped by the second superconductor 312). Dimensions of the Josephson Junction 314 along x-axis and y-axis, shown in FIG. 3C as dx and dv, respectively, are typically between about 50 and 1000 nm for any of dx and dy.

[0065] Furthermore, as a result of performing the double-angle shadow evaporation as described above, junctions of the first and second superconductors may also form on each side of the Josephson Junction 314, such junctions shown in FIGS. 3B and 3C as junctions 316. However, because these junctions are of much larger dimensions than the Josephson Junction 314, e.g.

measured several thousands of nm in the x-direction and hundreds of nm or more in the y-direction, they are essentially infinite for the Josephson effect to take place and, therefore, act as superconductors rather than Josephson Junctions.

[0066] As described above, one problem with such a fabrication approach is that making a robust electrical connection can be a challenge. For example, the Josephson Junction 314 is electrically connected to the conductive materials 320 of the supporting circuitry via small area sidewall connections, e.g. where the first superconductor 310 interfaces with the material 320 of a first supporting circuit element (on the right side of the view of FIG. 3C) and where the second superconductor 312 interfaces with the material 320 of a second supporting circuit element (on the left side of the view of FIG. 3C). A bilayer stack method disclosed herein may improve on at least some of the problems described above.

[0067] FIG. 4 provides a flow chart of a SC bilayer stack method 400 for fabricating quantum circuit assemblies with Josephson Junctions connected below the plane of supporting circuitry, according to some embodiments of the present disclosure.

[0068] Implementations of the present disclosure may be formed or carried out any substrate suitable for realizing quantum circuit assemblies described herein. In one implementation, the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.

[0069] Various operations of the method 400 may be illustrated with reference to two exemplary embodiments discussed below, but the method 400 may be used to manufacture any suitable quantum circuit assemblies with Josephson Junctions connected below the plane of supporting circuitry according to any embodiments of the present disclosure. FIGS. 5A-5H are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the SC bilayer stack method of FIG. 2 in accordance with a first embodiment of the present disclosure, while FIGS. 6A-6B are cross-sections illustrating various example stages in the manufacture of a quantum circuit assembly using the SC bilayer stack method of FIG. 2 in accordance with a second embodiment of the present disclosure. Each one of FIGS. 5A-5H and FIGS. 6A-6B illustrates a top down view of an assembly (i.e. a view in the x-y plane indicated in these FIGS.), a cross-sectional view of along the plane indicated with a horizontal dashed line shown in these FIGS. (i.e. a view in the z-y plane indicated in these FIGS.), and a cross-sectional view of along the plane indicated with a vertical dashed line shown in these FIGS. (i.e. a view in the z-x plane indicated in these FIGS.), where same reference numerals refer to the same or analogous elements/materials shown.

[0070] Although the operations of the method 400 are illustrated in FIG. 4 once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple quantum circuit assemblies as described herein substantially simultaneously. In another example, the operations may be performed in a different order to reflect the architecture of a particular quantum circuit component in which one or more quantum circuit assemblies with Josephson Junctions connected below the plane of supporting circuitry are to be included.

[0071] In addition, the manufacturing method 400 may include other operations, not specifically shown in FIG. 4, such as e.g. various cleaning operations as known in the art. For example, in some embodiments, the substrate may be cleaned prior to or/and after any of the processes of the bilayer stack method 400 described herein, e.g. to remove surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation

combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using hydrofluoric acid (HF)).

[0072] The method 400 may begin with providing a bilayer stack of conductive, e.g.

superconductive (SC) materials over a substrate (process 402 shown in FIG. 4, a result of which is illustrated with an assembly 502 shown in FIG. 5A). The assembly 502 illustrates a substrate 522, which could be any of the substrates described above, with a first conductive layer 524-1 provided over the substrate and a second conductive layer 524-2 provided over the first conductive layer. Together, the first and second conductive layers 524 form a bilayer stack 540 indicated in FIG. 5A.

[0073] In various embodiments, any suitable deposition techniques may be used for providing the bilayer stack 540 in the process 402, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating, and each of the first and second conductive layers 524 may include any conducting or superconducting material suitable for providing electrical connectivity in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting/conducting materials. For example, in some embodiments, providing the first conductive layer 524-1 over the substrate 522 may include depositing a conductive material, e.g. Al, of the first conductive layer using thermal evaporation, e-beam evaporation, or sputtering, while providing the second conductive layer 524-2 over the first conductive layer 524-1 may include depositing a conductive material, e.g. a material other than Al, of the second conductive layer using sputtering (e.g. using direct current (DC) or radio frequency (RF) sputtering for depositing Nb, or reactively sputtering NbN or NbTiN), PVD (e.g. to deposit Nb, NbN, NbTiN, or TiN), CVD, or ALD (e.g. to deposit Ti N). In other embodiments, the first and second conductive layers 524 may be made of the same material and deposited substantially in a single process, in which case the "first conductive layer" may refer to the lower portion of the bilayer stack 540, while the "second conductive layer" may refer to the upper portion of the bilayer stack 540.

[0074] In various embodiments, a thickness of the first conductive layer 524-1 (i.e. a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. GA-6B) provided in the process 402 may be between 5 and 200 nanometers, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm. In various embodiments, a thickness of the second conductive layer 524-2 (also a dimension measured along the z-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. 6A-6B) provided in the process 402 may be between about 50 and 500 nanometers, including all values and ranges therein, e.g. between about 100 and 250 nm.

[0075] The method may then proceed with patterning the upper SC layer, i.e. the conductive layer 524-2, to define supporting circuitry for a future Josephson Junction (process 404 shown in FIG. 4, a result of which is illustrated with an assembly 504 shown in FIG. 5B). FIG. 5B illustrates supporting circuitry in a form of a first conductive circuit element 542-1 and a second conductive circuit element 542-2, both defined by patterning the second conductive layer 524-2. In various embodiments, each of the first conductive circuit element and the second conductive circuit element is a portion of a conductive loop of a SQUID of a superconducting qu bit (i.e. a conductive, e.g. superconductive, loop containing two parallel Josephson Junctions used to tune the qubit frequency with a magnetic field that is applied using a flux bias line), a larger electrode for setting an overall capacitance of a qubit, or/and a port for capacitively coupling the Josephson Junction to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line. Once the Josephson Junction is formed, the first and second electrodes of the Josephson Junction (e.g. bottom and top electrodes) will be connected to a respective one of the first and second conductive circuit elements 542 using leads.

[0076] While the assembly 504 only illustrates the first and second conductive circuit elements 542 as examples of supporting circuitry, other conductive circuit elements may also be defined in the process 404 by patterning the second conductive layer 524-2, such as e.g. resonators (i.e. conductive circuit elements which will not necessarily be electrically connected to the Josephson Junction).

[0077] In various embodiments, any suitable patterning techniques may be used for defining the supporting circuitry 542 in the process 404, such as e.g. photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a dry etch, such as e.g. RF or inductively coupled plasma (ICP) reactive ion etch (RIE), to pattern the second conductive layer 524-2 into the specified geometries (i.e. etch in certain areas down to the first conductive layer 524-1) for a given implementation. If possible, in the embodiments when the first and second conductive layers 524 are made of different materials (etch-selective with respect to one another), a dry etch that provides a higher etch rate for the material of the second conductive layer 524-2 than for the material of the first conductive layer 524-1 may be chosen. For example, when the first conductive layer 524-1 is Al, a tetrafluoromethane (CF4) based etch for Nb and IMbN and NbTiN metals of the second conductive layer 524-2 may be chosen so that the dry etch stops on the first conductive layer 524-1 due to the difference in etch rates and thus is not as sensitive to etch times. In the embodiments when the first and second conductive layers 524 are made of the same material, defining the supporting circuitry 542 in the process 404 may include timed etch, where the timing is defined so that only the upper portion of the bilayer stack 540 (which, in these embodiments, comprises the same material as the "first" and "second" layers) is etched to define the supporting circuitry.

[0078] As is seen in FIG. 5B, patterning the upper SC layer 524-2 results in exposing portions of the lower SC layer, i.e. the first conductive layer 524-1 (i.e. the etch of the second conductive layer 524-2 in the process 404 is performed until the first conductive layer 524-1). The method 400 may then proceed with patterning at least a portion of the lower SC layer, i.e. the first conductive layer 524-1, exposed by the patterning of the process 404 to form leads for the future Josephson Junction (process 406 shown in FIG. 4). Geometry, dimensions, and orientation of the leads formed in the process 406 may take a number of different embodiments to form leads suitable for a particular Josephson Junction formed later on. Two such exemplary embodiments, i.e. two exemplary results of performing the process 406, are illustrated with an assembly 506 shown in FIG. 5C for a first embodiment of the present disclosure and with an assembly 606 shown in FIG. 6A for a second embodiment of the present disclosure. However, any other suitable implementations of leads in accordance with the principles described herein are within the scope of the present disclosure.

[0079] First, the method 400 will be described with the reference to the first embodiment as shown in FIGS. 5C-5H. After that, the second embodiment as shown in FIGS. 6A-6B will be described.

[0080] FIG. 5C illustrates the leads in a form of a first lead 544-1 and a second lead 544-2, both made of the first conductive layer 524-1, where the first lead 544-1 is electrically connected to the first conductive circuit element 542-1 and the second lead 544-2 is electrically connected to the second conductive circuit element 542-2. Patterning the first conductive layer 524-1 in the process 406 may be viewed as forming the first lead 544-1 by leaving an element of the first conductive layer, in the desired shape, extending from a portion of the first conductive layer which is under the first conductive circuit element 542-1 towards, but not contacting, the second conductive circuit element 542-2, while removing the rest of the first conductive layer material around such a lead. Similarly, the second lead 544-2 is formed by leaving an element of the first conductive layer, in the desired shape, extending from a portion of the first conductive layer which is under the second conductive circuit element 542-2 towards, but not contacting, the first conductive circuit element 542-1, while removing the rest of the first conductive layer material around such a lead. Thus, each of the first lead 544-1 and the second lead 544-2 may be implemented as a continuation of, or an integral part of, portions of the first conductive layer 524-1 extending from underneath, respectively, the first conductive circuit element 542-1 and the second conductive circuit element 542-2 in the directions towards one another.

[0081] Because such pairs of leads 544 extend away from the conductive circuit elements 542 but are typically of much smaller dimensions than the conductive circuit elements 542, they may be referred to as "fingers" or "stubs." For example, in various embodiments, a length of each of the first and second leads (i.e. a dimension measured along the y-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. 6A-6B) may be between about 100 and 10000 nm, including all values and ranges therein, e.g. between about 1000 and 5000 nm, or between about 1000 and 3000 nm.

[0082] The assembly 506 illustrates the first and second leads 544 to be of noticeably different widths (i.e. a dimension measured along the x-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. 6A-6B). Considerations for these dimensions will be described in greater detail below, when a Josephson Junction of the first embodiment is described.

[0083] Once the Josephson Junction is formed, the top and bottom electrodes of the Josephson Junction will be connected to a respective one of the first and second conductive circuit elements 542 using a respective one of the first and second leads 544.

[0084] In various embodiments, any suitable patterning techniques may be used for defining the leads 544 in the process 406, such as e.g. photolithographic or e-beam patterning, possibly in conjunction with a dry etch, such as e.g. RF or ICP RI E, to pattern the first conductive layer 524-1 into the specified geometries (i.e. etch in certain areas down to the substrate 522) for a given implementation.

[0085] The assembly 506 illustrates an embodiment where the first and second leads 544 are formed within an area 546 of the first conductive layer 524-1 exposed by patterning of the process 404, the area 546 being between the first and second conductive circuit elements 542, while the first conductive layer 524-1 outside of the area 546 remains. For example, the assembly 506 illustrates that the first conductive layer 524-1 remains in areas 548 and 550, indicated in FIG. 5C. In such an embodiment, a wet etch may then be used to remove the first conductive layer 524-1 in those areas, as illustrated in FIGS. 5D-5G and described below with optional processes 408-414 of the bilayer stack method 400 shown in FIG. 4. However, in other embodiments, the patterning of the process 406 may already result in the first conductive layer 524-1 being etched so that only the leads remain, as shown with an assembly 514 of FIG. 5G, in which case the wet etch is not necessary and the method 400 may then proceed to forming a Josephson Junction over the lead 544 (a process 416 shown in FIG. 4). For that reason, processes related to wet etch are labeled in FIG. 4 as optional.

[0086] In some implementations, using photo- or e-beam-lithography and dry etch only for forming the leads, while leaving the rest of the exposed first conductive layer 524-1 to be removed with a wet etch (i.e. in the implementations as shown with the assembly 506 in FIG. 5C) may be easier, from the fabrication perspective. In such implementations, the method 400 may then proceed with the wet etch to remove the rest of the areas of the first conductive layer 524-1 which were exposed in the process 404 when the supporting circuitry was defined. The wet etch may begin with providing a wet etch protection over the leads 544 (a process 408 shown in FIG. 4, a result of which is illustrated with an assembly 508 shown in FIG. 5D). While the assembly 508 illustrates a wet etch protection as an etch protective layer 526 provided over the leads 544 and shaped as a rectangle, in other embodiments, the etch protective layer 526 may take any other shapes or forms, as long as it sufficiently covers the leads 544 to protect them from the etchants of the wet etch process applied subsequently, while leaving the portions of the first conductive layer 524-1 which need to be removed exposed (i.e. without the etch protective layer). As shown in the example of FIG. 5D, in some embodiments, the etch protective layer 526 may extend to cover portions of the second conductive layer 524-2, but does not have to do so because the wet etch chemistry applied can be selected such that it does not substantially etch the material of the second conductive layer 524-2. In other embodiments, the etchants can be selected such that an etch for the material of the first conductive layer 524-1 has a higher etch rate than that for the material of the second conductive layer 524-2.

[0087] In some embodiments, covering the first and second leads 544 with an etch protective layer such as the layer 526 may include providing a photosensitive or e-beam sensitive polymer or photoresist that may directly act as a mask or a protection layer, or providing a mask or protection layer that is patterned or defined by a lithographic process that patterns this mask or protection layer. The mask or protection layer is any layer that protects that covered portion of the circuitry from the etch process which can be a wet etch or an isotropic dry etch that is capable of accomplishing the undercut, in case the undercut of the supporting circuitry is desired, as described below.

[0088] The method 400 may then proceed with performing a wet etch protection to remove portions of the first conductive layer 524-1 which were exposed when the supporting circuitry was patterned in the process 404 and which are not protected with the etch protective layer in the process 408 (a process 410 shown in FIG. 4, a result of which is illustrated with an assembly 510 shown in FIG. 5E). In various embodiments, any suitable etchants may be used for removing portions of the first conductive layer 524-1 in the process 410, as long as etchants will not etch the substrate 522 (i.e. the etch will stop at the substrate 522) so that issues associated with over-etching into a substrate may be circumvented. For example, in some embodiments, an etchant used in the process 410 may include approximately 2% tetramethylammonium hydroxide (TMAH), in case the first conductive layer 524-1 includes Al.

[0089] FIG. 5E illustrates two cross-sections in the x-z plane (on the right side of the FIG.), where the bottom cross-section x-z illustrates that, in some embodiments, the wet etch may be performed just long enough to etch the first conductive layer 524-1 down to the substrate so that the first conductive layer 524-1 adapts to the shapes of the supporting circuitry defined in the second conductive layer 524-2 in the process 404, described above. This is shown in the bottom cross-

section x-z of FIG. 5E with the sidewalls 546 of the underlying portions of the first conductive layer 524-1 being substantially aligned with the sidewalls 548 of the second conductive layer 524-2 in which supporting circuitry exemplified by the first and second conductive elements 542 was defined.

[0090] On the other hand, FIG. 5F illustrates an optional embodiment of an assembly 512 similar to the assembly 510 shown in FIG. 5E but the assembly 512 being a result of continuing the wet etch of the process 410 so that the material of the first conductive layer 524-1 is undercut under the supporting circuitry defined in the second conductive layer 524-2 (an optional process 412 shown in FIG. 4). This is shown in the bottom cross-section x-z of FIG. 5F with the sidewalls 546 of the underlying portions of the first conductive layer 524-1 being recessed by a depth du (a dimension measured along the x-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. 6A-6B; where subscript "u" stands for "undercut") with respect to the sidewalls 548 of the second conductive layer 524-2 in which supporting circuitry exemplified by the first and second conductive elements 542 was defined. In various embodiments, the undercut depth du may be between about 0 and 1000 nm, including all values and ranges therein, e.g. between about 10 and 200 nm, or between about 20 and 100 nm. In various embodiments, the undercut depth du may be between about 1% and 40% of the width of the conductive circuit element as defined by the second conductive layer 524-2 being undercut, including all values and ranges therein, e.g. between about 5 and 25 %, or between about 10 and 20 %.

[0091] An appropriate etchant may be selected to create a desired undercut du. For example etchant that has a higher etch rate for the first conductive layer 524-1 than for the second conductive layer 524-2. For example, in the case of the first conductive layer 524-1 being Al under a Nb based material of the second conductive layer 524-2, 2% TMAH may be used to selectively etch Al to create an undercut as illustrated in FIG. 5F.

[0092] Creating such undercuts under supporting circuitry elements may be particularly advantageous for superconducting qubits in terms of spurious TLS's, as explained below.

[0093] One major source of loss and thus decoherence in superconducting qubits is thought to be attributable to spurious TLS's in the areas surrounding Josephson Junctions, in particular, TLS's in dielectric materials which are not highly crystalline, such as e.g. the substrates on which quantum circuits are often built. These TLS's are thought to be either an electron or an ion that can tunnel between two spatial states, which are caused either by defects in the crystal structure of the substrate or through polar impurities such as hydroxyl (OH- ) groups. One mechanism of how spurious TLS's can lead to decoherence in a qubit is based on the idea that, if the TLS's are in a close proximity to the qubit and are in resonance with the qubit (i.e. when the frequency of a spurious TLS is close to the frequency of a qubit), they can couple to it. When this happens, spurious TLS's and the qubit exchange energy in the form of photons emitted by the qubit and absorbed by the spurious TLS's and may be viewed as a spurious TLS-qubit system having a certain combined energy. When combined energy of such a TLS-qubit system decays through phonon emission from the spurious TLS's, the TLS-qubit system relaxes, leading to decoherence of the qubit. Spurious TLS's that lead to qubit decoherence by this mechanism may be present at the surface of superconductive materials (i.e. TLS's present at the supeconductor-air interface) or/and at an interface between the substrate 522 and the superconductive bilayer stack 540. This problem is thought to be made even worse at areas of higher concentration of electromagnetic fields, which are typically areas around sharp corners/angles at metal/dielectric interfaces (i.e. at the interfaces of an electrically conductive materials of the supporting circuitry and the dielectric material of the substrate, or air.)

[0094] Embodiments of the present disclosure which include the undercut are based on an insight that the density of spurious TLS's at superconductor-substrate interfaces is higher than that at superconductor-air interfaces and therefore, in general, minimizing superconductor-substrate interfaces may be beneficial for extending qubit coherence times. Consequently, reducing the interface area between a substrate and bottom superconductive portions of supporting circuitry may reduce the total amount of spurious TLS's in close proximity to qubits and, thus, could improve on the decoherence problems qubits. Suspending portions of the supporting circuitry over the substrate 522 by virtue of creating undercuts in the first conductive layer 524-1 with respect to the second conductive layer 524-2 allows reducing the combined areas of the substrate-superconductor interface and also moves the sharp angles/corners of the superconductor (i.e. areas of higher electric field) further away from the lossy substrate, which should reduce coupling to the spurious TLS's due to the presence of the substrate 522 and reduce loss in the microwave region. As a result, coherence times of superconducting qubits may be improved.

[0095] Creating such undercuts may be particularly beneficial for resonators (i.e. a particular type of supporting circuitry, although not specifically illustrated in FIGS. 5A-5H and FIGS. 6A-6B) in that it may advantageously improve resonator quality factor. Such resonators may be fabricated in a manner as explained with reference to the first and second conductive circuit elements 542, except that resonators are implemented with conductive circuit elements which are not electrically connected to Josephson Junctions. In some embodiments, each such resonator may be implemented as a coplanar waveguide (CPW) comprising conductive circuit elements in the form of a signal line with a ground plane on each side of the signal line, where the signal line may be undercut as described herein. In other words, a width of the upper portion of the signal line (i.e. the portion of the signal line formed from the second conductive layer 524-2) is greater than a width of the lower portion of the signal line (i.e. the portion of the signal line formed from the first

conductive layer 524-1). In this manner, along a length of the signal line of a resonator, a portion of the upper portion of the signal line is suspended over the substrate 522 on each side of the lower portion of the signal line. Thus, an area, in a plane parallel to the plane of the substrate 522, of the upper portion of the resonator is greater than an area, also in a plane parallel to the plane of the substrate, of the lower portion of the resonator. The ground planes of the CPW resonator may be undercut as well.

[0096] As a result of creating the undercut because of uneven removal of the material of the first conductive layer 524-1 compared to the material of the second conductive layer 524-2, portions of the supporting circuitry such as e.g. the first and second conductive circuit elements 542 or any of the resonators (not specifically shown in FIG. 5F), may be suspended at a distance to the substrate 522 that is equal to the thickness of the first conductive layer 524-1, i.e. between about 5 and 200 nm.

[0097] Once portions of the first conductive layer 524-1 exposed by patterning of the second conductive layer 524-2 but not protected with the etch protective layer 526 are removed, either with or without the undercut as described above, the method 400 may proceed with the removal of the etch protective layer 525 (a process 414 shown in FIG. 4, a result of which is illustrated with an assembly 514 shown in FIG. 5G). In various embodiments, any suitable techniques for removing the etch protective layer 526 may be employed, such as dissolving an organic-based protection layer in an appropriate organic solvent such as warm acetone or Gensolve (NMP-based solvent).

[0098] While embodiments of processes 408-414 described above and illustrated in FIG. 4 refer to wet etch, in other embodiments, isotropic dry etch may be used, alternatively or in addition to the wet etch, to remove portions of the first conductive layer 524-1 exposed by patterning of the second conductive layer 524-2 but not protected with the etch protective layer 526. In particular, isotropic dry etch may also be used to create undercuts as described above, either on its' own or following the wet etch to remove portions of the first conductive layer 524-1 exposed by patterning of the second conductive layer 524-2 but not protected with the etch protective layer 526.

[0099] Turning back to FIG. 4, the method 400 may then proceed to forming a Josephson Junction connected to the first and second leads 544 (a process 416 shown in FIG. 4). Such a Josephson Junction may e.g. be a part of a SQU ID of a superconducting qubit.

[0100] In a first embodiment, a Josephson Junction 550 shown with an assembly 516 in FIG. 5H may be formed, having a bottom electrode electrically connected to the first lead 544-1 and a top electrode electrically connected to the second lead 544-2. Such a Josephson Junction may be formed by providing a layer of oxide 528 over at least a portion of the first lead 544-1, and then depositing a strip of conductive (e.g. superconductive) material 530 over a portion of the second

lead and over the layer of oxide provided over the portion of the first lead. In this manner, a Josephson Junction is created where a portion 552 of the first lead forms a bottom electrode of the Josephson Junction, and a portion 554 of the conductive material 530 that opposes the portion 552 forms a top electrode of the Josephson Junction, with the portion of oxide 528 in between being the tunnel barrier of the Josephson Junction. This is where the relative dimensions of the first and second leads 544 come into play, as explained below.

[0101] In order for Josephson effect to take place, the dimensions of the Josephson Junction in the plane parallel to the plane of the substrate 522 should be relatively small. Otherwise Josephson Junction will simply act as a conductor, as was explained above with reference to the junctions 314 and 316 shown in FIGS. 3B and 3C. Since in the embodiment illustrated in FIG. 5H, a Josephson Junction is provided over one of the leads, that means that a portion of the lead over which the Josephson Junction is to be provided should be relatively small. For that reason, a width of a portion of the first lead 544-1 over which portion the Josephson Junction is to be provided (a dimension measured along the x-axis of the coordinate system as shown in FIGS. 5A-5H and FIGS. 6A-6B) should be below approximately 500 nm, including all values and ranges therein, e.g. between about 20 and 300 nm, or between about 50 and 150 nm. Thus, in such implementations, only the portion of the first lead on which a Josephson Junction will be formed (i.e. only the portion of the first lead which will form the bottom electrode of a Josephson Junction) should have a width below the maximum width described above. Everywhere else the dimensions of the first lead 544-1 can be relaxed and can be greater than this dimension. In particular, while FIGS. 5C-5H illustrate an embodiment where the first lead 544-1 has the same width throughout the lead, in other embodiments, this may not be the case. For example, the first lead 544-1 may be wider at its portion where it is closer to the first conductive circuit element 542-1, and then become narrower as it extends towards the second conductive circuit element 542-2. Such a first lead would be advantageous because it would allow providing a sufficiently small area for the Josephson effect to take place at one part of it (namely, where the Josephson Junction will be formed), while providing a sufficiently large area for making contact to the supporting circuitry at another part of the lead. On the other hand, the second lead 544-2, connecting to the top electrode of the Josephson Junction 550, may have a constant width, and that width may be greater than the maximum set for the width of the first lead 544-1. For example, in some embodiments, a width of the second lead 544-2 may be above approximately 500 nm, including all values and ranges therein, e.g. between about 500 and 5000 nm, or between about 1000 and 2000 nm.

[0102] In various embodiments, a distance between the overlapping portions of the first and second leads 544 may be between about 25 and 5000 nm, including all values and ranges therein, e.g. between about 50 and 500 nm.

[0103] Turning back to forming the Josephson Junction 550, providing the layer of oxide 528 over at least the portion of the first lead 544-1 may include performing a controlled oxidation process to oxidize a layer at the exposed upper, and possibly sidewall, surface(s) of the conductive material of the first lead. Generally, a layer of oxide to serve as a tunnel barrier of a Josephson Junction in this case may be provided as a two-step process. In the first step, inferior-quality surface oxide is removed (i.e. surface oxide which may have formed spontaneously, i.e. uncontrollably, in previous steps and/or exposure to ambient conditions), e.g. using a light sputtering step such as e.g. argon (Ar) sputtering. In the second step which follows the first step, good-quality surface oxide of controlled thickness and quality is grown with a controlled oxidation step in substantially pure oxygen, e.g. 1-10 minutes in substantially pure oxygen at a pressure of about .1 - 1 millibar, where the exact time and pressure may be selected so as to set the oxide thickness and quality of the oxide and thus the desired resistance of the Josephson Junction, in conjunction with its area, and thereby set the frequency of the qubit, in conjunction with the charging energy Ec and the Josephson energy Ej for the particular qubit design.

[0104] In various embodiments, a thickness of the oxide 528 may be between approximately 0.3 and 3 nm, including all values and ranges therein, e.g. between about 0.5 and 1.8 nm, or between about 1 and 1.7 nm.

[0105] The strip of conductive material 530 may then be deposited using any standard deposition technique, such as e.g. thermal evaporation, e-beam evaporation, or any other PVD process, and may include any suitable conductive/superconductive material as described above.

[0106] A second embodiment of forming a Josephson Junction connected to the first and second leads 544 in the process 416 shown in FIG. 4 may be explained with reference to FIGS. 6A-6B, where the same reference numerals as those shown in FIGS. 5A-5H are intended to indicate the same or analogous elements, a description of which is, therefore, not repeated. FIG. 6A illustrates an assembly 606 which may be a result of performing the process 406 according to this embodiment of the present disclosure. As shown in FIG. 6A, in such an embodiment, the first and second leads 544 may be substantially opposite one another, instead of being partially overlapping as was shown with the embodiment of the assembly 506 in FIG. 5C. As shown in an assembly 616 in FIG. 6B, in such an embodiment, as a result of the process 416, a Josephson Junction 650 may be formed between the first and second leads 544, e.g. using double-angle shadow evaporation, described above. In this process, first, a conductive material 630 may be deposited at a first angle, similar to the deposition of the conductive material 310 shown in FIG. 3A (a hanging resist mask or other details for the double-angle shadow evaporation is not shown in FIG. 6B). Then surface of that material is oxidized, creating a layer of oxide 528. Next, a conductive material 530 may be deposited at a second angle, similar to the deposition of the conductive material 312 shown in FIG. 3B.

[0107] In the embodiment shown in FIG. 6B, the first and second leads can be both of substantially the same dimensions and oriented in a variety of ways. A resulting Josephson Junction 650 is then connected to the supporting circuitry with a relatively large area (e.g. areas 652-2 and 652-1 shown in FIG. 6B) from under the supporting circuitry rather than relying on a sidewall connection as is the case with many conventional implementations of double-angle shadow evaporation, as was explained with reference to FIG. 3C.

[0108] To summarize, various embodiments of employing the bilayer fabrication method described above result in quantum circuit assemblies where the first and second conductive circuit elements 542 are provided over the substrate 522, each conductive circuit element 542 having an upper portion (i.e. the portion corresponding to the second conductive layer 524-2) and a lower portion (i.e. the portion corresponding to the first conductive layer 524-2). A first and second leads 544 for a future Josephson Junction are also provided, the first lead 544-1 connected to the first conductive circuit element 542-1 and the second lead 544-2 connected to the second conductive circuit element 542-2. The Josephson Junction 550, 650 is subsequently provided over the substrate 522 and electrically connected to the first and second conductive circuit elements 542 via the first and second leads 544 in a manner such that the first lead 544-1 electrically connects a bottom electrode of the Josephson Junction to the lower portion of the first conductive circuit element 542-1 and the second lead 544-2 electrically connects a top electrode of the Josephson Junction to the lower portion of the second conductive circuit element 542-2. The first and second leads 544 and the lower portion of each of the first and second conductive circuit elements 542 are in a first plane above the substrate 522, while the upper portion of each of the first and second conductive circuit elements 542 is in a second plane above the substrate 522, the second plane being above the first plane. Supporting circuitry besides the first and second conductive circuit elements 542 not electrically connected to the Josephson Junction, such as e.g. resonators provided over the substrate 522, may also be viewed as having an upper portion and a lower portion as described for the first and second conductive circuit elements 542. The lower portion of such resonators is in said first plane and the upper portion of such resonators is in said second plane.

[0109] The different views of the quantum circuit assemblies with Josephson Junctions connected below the plane of supporting circuitry as described herein are shown in the FIGS, with precise right angles and straight lines, which does not reflect example real world process limitations which may cause the features to not look so ideal when any of the structures described above are examined using e.g. scanning electron microscopy (SEM) images or transmission electron miscroscope (TEM) images. In such images of real structures, possible processing defects could also be visible, such as e.g. tapered vias, occasional screw, edge, or combination dislocations within the crystalline region, occasional dislocation defects of single atoms or clusters of atoms.

Exemplary pubit devices

[0110] Quantum circuit assemblies/structures as described above may be included in any kind of qubit devices or quantum processing devices/structures. Some examples of such devices/structures are illustrated in FIGS. 7A-7B, 8, and 9.

[0111] FIGS. 7A-7B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits disclosed herein, e.g., the quantum circuit 100, and may include any of the quantum circuit assemblies described herein, such as e.g. the quantum circuit assembly 316, the quantum circuit assembly 415, any combinations of these assemblies, or any further embodiments of these assemblies as described herein (e.g. with alternative geometries/dimensions for the leads). The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. A die 1102 may include one or more quantum circuits 100, including any supporting conductive circuitry to route electrical signals within the quantum circuits 100 (e.g., the first and second conductive circuit elements connected to the first and second leads of a Josephson Junction as described herein), as well as any other IC components. In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 9) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0112] FIG. 8 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuit assemblies disclosed herein. The device assembly 1200 includes a number of components disposed on a circuit board 1202. The device assembly 1200 may

include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.

[0113] In some embodiments, the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. In other embodiments, the circuit board 1202 may be a package substrate or flexible board.

[0114] The IC device assembly 1200 illustrated in FIG. 8 may include a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216. The coupling components 1216 may electrically and mechanically couple the package-on-interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG. 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0115] The package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218. The coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 8, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204. The interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220. The package 1220 may be a quantum circuit device package as described herein, e.g. a package including the quantum circuit 100 with any of the quantum circuit assemblies as described herein, or a combination thereof, or may be a conventional IC package, for example. Generally, the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202. In the embodiment illustrated in FIG. 8, the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204. In some embodiments, three or more components may be interconnected by way of the interposer 1204.

[0116] The interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials

described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206. The interposer 1204 may further include embedded devices 1214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.

[0117] The device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222. The coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216, and the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220. The package 1224 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein.

[0118] The device assembly 1200 illustrated in FIG. 8 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228. The package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232. The coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above. Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional IC package, for example. In some embodiments, one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit 100 with any of the quantum circuit assemblies described herein, or a combination thereof.

[0119] FIG. 9 is a block diagram of an exemplary quantum computing device 2000 that may include any of the quantum circuits with any of the quantum circuit assemblies disclosed herein. A number of components are illustrated in FIG. 9 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000

may be attached to one or more PCBs (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with any of the quantum circuit assemblies described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 9, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.

[0120] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuits 100 with any of the quantum circuit assemblies disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.

[0121] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic

to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[0122] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0123] The quantum computing device 2000 may include a cooling apparatus 2024. The cooling apparatus 2024 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0124] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the

quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0125] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the I EEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless

communications (such as AM or FM radio transmissions).

[0126] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip

2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[0127] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[0128] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0129] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0130] The quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above). The audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MI DI) output).

[0131] The quantum computing device 2000 may include a GPS device 2016 (or corresponding interface circuitry, as discussed above). The GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[0132] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0133] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (Q.R) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0134] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal

computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

Select Examples

[0135] The following paragraphs provide examples of various ones of the embodiments disclosed herein.

[0136] Example 1 provides a quantum circuit assembly that includes a first conductive circuit element and a second conductive circuit element provided over a substrate, each having an upper portion and a lower portion, and a Josephson Junction provided over the substrate and electrically connected to the first and second conductive circuit elements via a first lead and a second lead, where the first lead electrically connects a first electrode (e.g. the bottom electrode) of the Josephson Junction to the lower portion of the first conductive circuit element, and the second lead electrically connects a second electrode (e.g. the top electrode) of the Josephson Junction to the lower portion of the second conductive circuit element.

[0137] Example 2 provides the quantum circuit assembly according to Example 1, where the upper portion and the lower portion of each of the first conductive circuit element and the second conductive circuit element are made of different electrically conductive, e.g. superconductive, materials. In such an Example, the manufacturing process would rely on different etch selectivity of the different conductive materials for the lower and the upper portions of the conductive circuit elements.

[0138] Example 3 provides the quantum circuit assembly according to Example 2, where the lower portion of each of the first conductive circuit element and the second conductive circuit element includes Al, and the upper portion of each of the first conductive circuit element and the second conductive circuit element includes Nb, NbN, TiN, or NbTiN, or some other electrically conductive, e.g. superconductive, material, different from Al.

[0139] Example 4 provides the quantum circuit assembly according to Example 1, where the upper portion and the lower portion of each of the first conductive circuit element and the second conductive circuit element are made of a same material. In such an Example, the manufacturing process would rely on a timed etching process for forming the conductive circuit elements and the leads.

[0140] Example 5 provides the quantum circuit assembly according to any one of the preceding Examples, where each of the first lead, the second lead, and the lower portion of each of the first conductive circuit element and the second conductive circuit element is in a first plane above the substrate, and the upper portion of each of the first conductive circuit element and the second

conductive circuit element is in a second plane above the substrate, the second plane being above the first plane.

[0141] Example 6 provides the quantum circuit assembly according to Example 5, further including a resonator provided over the substrate, the resonator having an upper portion and a lower portion.

[0142] Example 7 provides the quantum circuit assembly according to Example 6, where the lower portion of the resonator is in the first plane and the upper portion of the resonator is in the second plane.

[0143] Example 8 provides the quantum circuit assembly according to Examples 6 or 7, where an area, in a plane parallel to the plane of the substrate, of the upper portion of the resonator is greater than an area, also in a plane parallel to the plane of the substrate, of the lower portion of the resonator.

[0144] Example 9 provides the quantum circuit assembly according to any one of Examples 6-8, where the resonator is a CPW including a signal line, where a width of the upper portion of the signal line is greater than a width of the lower portion of the signal line.

[0145] Example 10 provides the quantum circuit assembly according to Example 9, where, along a length of the signal line, a portion of the upper portion of the signal line is suspended over the substrate on each side of the lower portion of the signal line.

[0146] Example 11 provides the quantum circuit assembly according to Example 10, where a distance between the substrate and the portion of the upper portion of the signal line suspended over the substrate on each side of the lower portion of the signal line is between 5 and 200 nanometers. Thus, a thickness of the bottom layer, e.g. Al layer, of a bilayer stack as described herein may be between about 5 and 200 nm.

[0147] Example 12 provides the quantum circuit assembly according to any one of the preceding Examples, where each of the first conductive circuit element and the second conductive circuit element is a portion of a conductive loop of a SQUID of a superconducting qubit (i.e. a conductive, e.g. superconductive, loop containing two parallel Josephson Junctions used to tune the qubit frequency with a magnetic field that is applied using a flux bias line), a larger electrode for setting an overall capacitance of a qubit, or/and a port for capacitively coupling to one or more of a readout resonator, a coupling resonator, and a direct microwave drive line.

[0148] Example 13 provides the quantum circuit assembly according to any one of the preceding Examples, where a thickness of the lower portion of each of the first conductive circuit element and the second conductive circuit element is between about 5 and 200 nm, including all values and ranges therein, e.g. between about 5 and 100 nm, or between about 5 and 35 nm. Since, according to the bilayer method described herein, the lower portions of the first and second conductive circuit elements are made of the bottom layer, e.g. Al layer, of a bilayer stack as described herein, these thickness ranges correspond to the thickness ranges for the bottom layer of the bilayer stack described herein, e.g. the first conductive layer 524-1.

[0149] Example 14 provides the quantum circuit assembly according to any one of the preceding Examples, where a thickness of the upper portion of each of the first conductive circuit element and the second conductive circuit element is between 50 and 500 nanometers, including all values and ranges therein, e.g. between 100 and 250 nm. Since, according to the bilayer method described herein, the upper portions of the first and second conductive circuit elements are made of the top layer, e.g. non-AI layer, of a bilayer stack as described herein, these thickness ranges correspond to the thickness ranges for the top layer of the bilayer stack described herein, e.g. the second conductive layer 524-2.

[0150] Example 15 provides the quantum circuit assembly according to any one of the preceding Examples, where the first lead includes a portion (e.g. a strip or a "finger"/" stub") of a material of the lower portion of the first conductive circuit element extending from the lower portion of the first conductive circuit element towards the second conductive circuit element, and the second lead includes a portion (e.g. a strip or a "finger"/"stub") of a material of the lower portion of the second conductive circuit element extending from the lower portion of the second conductive circuit element towards the first conductive circuit element.

[0151] Example 16 provides the quantum circuit assembly according to Example 15, where a distance between the portion of the material of the lower portion of the first conductive circuit element extending from the lower portion of the first conductive circuit element towards the second conductive circuit element and the portion of the material of the lower portion of the second conductive circuit element extending from the lower portion of the second conductive circuit element towards the first conductive circuit element is between about 25 and 5000 nm, including all values and ranges therein, e.g. between about 50 and 500 nm. In various embodiments, a length of each of the first and second leads may be between about 100 and 10000 nm, including all values and ranges therein, e.g. between about 1000 and 5000 nm, or between about 1000 and 3000 nm.

[0152] Example 17 provides the quantum circuit assembly according to any one of the preceding Examples, where the Josephson Junction is provided over a portion of the first lead, and a width of said portion of the first lead is below about 500 nm, including all values and ranges therein, e.g. between about 20 and 300 nm, or between about 50 and 150 nm.

[0153] Example 18 provides the quantum circuit assembly according to any one of the preceding Examples, where a width of the second lead is above about 500 nm, including all values and ranges therein, e.g. between about 500 and 5000 nm, or between about 1000 and 2000 nm.

[0154] Example 19 provides the quantum circuit assembly according to any one of Examples 1-15, where the Josephson Junction is provided between the first lead and the second lead.

[0155] Example 20 provides the quantum circuit assembly according to any one of the preceding Examples, where the Josephson Junction is a part of a SQUID of a superconducting qubit.

[0156] Example 21 provides a method of fabricating a quantum circuit assembly. The method includes providing a first conductive layer over a substrate and a second conductive layer over the first conductive layer (i.e. forming a bilayer stack of conductive materials over the substrate);

patterning the second conductive layer to define (i.e. begin forming) supporting circuitry for a future Josephson Junction, the supporting circuitry including at least a first conductive circuit element and a second conductive circuit element out of the material of the second conductive layer; patterning a portion of the first conductive layer exposed by patterning the second conductive layer to form a first lead electrically connected to the first conductive layer and a second lead electrically connected to the second conductive circuit element, the first lead and the second lead being formed out of the material of the first conductive layer; and forming a Josephson Junction having a bottom electrode electrically connected to the first lead and a top electrode electrically connected to the second lead.

[0157] Example 22 provides the method according to Example 21, where patterning the portion of the first conductive layer includes forming the first lead extending from a portion of the first conductive layer under the first conductive circuit element and forming a second lead extending from a portion of the first conductive layer under the second conductive circuit element.

[0158] Example 23 provides the method according to Examples 21 or 22, where a portion of the first conductive layer exposed by patterning the second conductive layer is a first portion, the method further including covering the first lead and the second lead with an etch protective layer; and performing an etch to remove a second portion of the first conductive layer exposed by patterning the second conductive layer.

[0159] Example 24 provides the method according to Example 23, further including continuing to perform the etch (e.g. wet or dry etch, e.g. isotropic dry etch) to remove a portion of the first conductive layer under the first conductive circuit element and under the second conductive circuit element, thus creating an undercut of depth du under the first and second conductive circuit elements.

[0160] Example 25 provides the method according to Examples 23 or 24, where performing the etch includes performing an etch that has a higher etch rate for the first conductive layer than for the second conductive layer, e.g. in the case of Al under a Nb based material using about 2% TMAH to selectively etch Al to create an undercut.

[0161] Example 26 provides the method according to any one of Examples 21-25, where providing the first conductive layer over the substrate includes depositing a conductive material (e.g. Al) of the first conductive layer using thermal evaporation, e-beam evaporation, or sputtering.

[0162] Example 27 provides the method according to any one of Examples 21-26, where providing the second conductive layer over the first conductive layer includes depositing a conductive material (e.g. a material other than Al) of the second conductive layer using sputtering (e.g. using DC or RF sputtering for depositing Nb, or reactively sputtering NbN or NbTiN), PVD (e.g. to deposit Nb, NbN, NbTiN, or ΤΪΝ), CVD, or ALD (e.g. to deposit TiN).

[0163] Example 28 provides the method according to any one of Examples 21-27, where patterning the second conductive layer to form the first conductive circuit element and the second conductive circuit element includes using standard photo-lithography or e-beam-lithography processes, possibly in conjunction with a dry etch.

[0164] Example 29 provides the method according to any one of Examples 21-28, where patterning the portion of the first conductive layer exposed by patterning the second conductive layer to form the first lead and the second lead includes using standard photo-lithography or e-beam-lithography processes, possibly in conjunction with a dry etch, e.g. RF or ICP RIE and/or in conjunction with using a wet etch, e.g. 2% TMAH to pattern Al, to pattern the first conductive layer into the specified geometries for a given implementation. In case a wet etch is used for this process, the etch stops on the substrate and so issues associated with over-etching into a substrate with timed dry etches may be circumvented.

[0165] Example 30 provides the method according to any one of Examples 21-29, where forming the Josephson Junction includes providing a layer of oxide over at least a portion of the first lead; and depositing a strip of conductive material over a portion of the second lead and over the layer of oxide provided over the portion of the first lead.

[0166] Example 31 provides the method according to Example 30, where providing the layer of oxide over at least the portion of the first lead includes performing a controlled oxidation process to oxidize a layer at the exposed upper and sidewall surface(s) of the conductive material of the first lead.

[0167] Example 32 provides the method according to Examples 30 or 31, where a thickness of the layer of oxide over the portion of the first lead is between about 0.3 and 2 nanometers, including all values and ranges therein, e.g. between about 0.5 and 1.8 nm, or between about 1 and 1.7 nm.

[0168] Example 33 provides the method according to any one of Examples 30-32, where depositing the strip of conductive material includes performing PVD, e.g. thermal evaporation, e-beam evaporation, or any other PVD process.

[0169] Example 34 provides the method according to any one of Examples 21-29, where forming the Josephson Junction includes forming the Josephson Junction between the first and the second leads using double-angle shadow evaporation.

[0170] Example 35 provides a quantum computing device that includes a quantum processing device and a memory device. The quantum processing device includes a substrate and a plurality of qubits disposed over or in the substrate, where at least one qubit of the plurality of qubits includes a first conductive circuit element and a second conductive circuit element provided over the substrate, each having an upper portion and a lower portion, and a Josephson Junction provided over the substrate and electrically connected to the first and second conductive circuit elements via a first lead and a second lead, wherein the first lead electrically connects a bottom electrode of the Josephson Junction to the lower portion of the first conductive circuit element, and the second lead electrically connects a top electrode of the Josephson Junction to the lower portion of the second conductive circuit element. The memory device is configured to store data generated by the plurality of qubits during operation of the quantum processing device.

[0171] Example 36 provides the quantum computing device according to Example 35, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

[0172] Example 37 provides the quantum computing device according to Examples 35 or 36, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0173] Example 38 provides the quantum computing device according to any one of Examples 35-37, further including a non-quantum processing device coupled to the quantum processing device.

[0174] In further Examples, the quantum processing device of the quantum computing device according to any one of Examples 35-38 may include a quantum circuit assembly according to any one of Examples 1-20, and/or at least portions of the quantum processing device of the quantum computing device may be fabricated using the method according to any one of Examples 21-34.

[0175] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0176] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.