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1. (WO2019032115) QUBIT DEVICES WITH JOSEPHSON JUNCTIONS CONNECTED BELOW SUPPORTING CIRCUITRY
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Claims:

1. A quantum circuit assembly comprising:

a substrate;

a first conductive circuit element and a second conductive circuit element over the substrate, each having an upper portion and a lower portion; and

a Josephson Junction over the substrate and electrically connected to the first and second conductive circuit elements via a first lead and a second lead, wherein:

the first lead electrically connects a first electrode of the Josephson Junction to the lower portion of the first conductive circuit element, and

the second lead electrically connects a second electrode of the Josephson Junction to the lower portion of the second conductive circuit element.

2. The quantum circuit assembly according to claim 1, wherein the upper portion and the lower portion of each of the first conductive circuit element and the second conductive circuit element are made of different conductive materials.

3. The quantum circuit assembly according to claim 1, wherein the upper portion and the lower portion of each of the first conductive circuit element and the second conductive circuit element are made of a same material.

4. The quantum circuit assembly according to claim 1, wherein each of the first lead, the second lead, and the lower portion of each of the first conductive circuit element and the second conductive circuit element is in a first plane above the substrate, and the upper portion of each of the first conductive circuit element and the second conductive circuit element is in a second plane above the substrate, the second plane being above the first plane.

5. The quantum circuit assembly according to claim 4, further comprising a resonator over the substrate, the resonator having an upper portion and a lower portion, wherein the lower portion of the resonator is in the first plane and the upper portion of the resonator is in the second plane.

6. The quantum circuit assembly according to claim 5, wherein the resonator is a coplanar waveguide (CPW) comprising a signal line, wherein a width of the upper portion of the signal line is greater than a width of the lower portion of the signal line.

7. The quantum circuit assembly according to claim 6, wherein, along a length of the signal line, a portion of the upper portion of the signal line is suspended over the substrate on each side of the lower portion of the signal line.

8. The quantum circuit assembly according to claim 7, wherein a distance between the substrate and the portion of the upper portion of the signal line suspended over the substrate on each side of the lower portion of the signal line is between 5 and 200 nanometers.

9. The quantum circuit assembly according to any one of claims 1-8, wherein each of the first conductive circuit element and the second conductive circuit element is a portion of a conductive loop of a superconducting quantum interference device (SQUID), an electrode for setting an overall capacitance of a qubit, or/and a port for capacitively coupling to one or more of a readout resonator, a coupling resonator, and a microwave drive line.

10. The quantum circuit assembly according to any one of claims 1-8, wherein a thickness of the lower portion of each of the first conductive circuit element and the second conductive circuit element is between 5 and 200 nanometers.

11. The quantum circuit assembly according to any one of claims 1-8, wherein a thickness of the upper portion of each of the first conductive circuit element and the second conductive circuit element is between 50 and 500 nanometers.

12. The quantum circuit assembly according to any one of claims 1-8, wherein the first lead comprises a portion of a material of the lower portion of the first conductive circuit element extending from the lower portion of the first conductive circuit element towards the second conductive circuit element, and the second lead comprises a portion of a material of the lower portion of the second conductive circuit element extending from the lower portion of the second conductive circuit element towards the first conductive circuit element.

13. The quantum circuit assembly according to any one of claims 1-8, wherein the Josephson Junction is over a portion of the first lead, and a width of said portion of the first lead is below 500 nanometers.

14. The quantum circuit assembly according to any one of claims 1-8, wherein a width of the second lead is above 500 nanometers.

15. The quantum circuit assembly according to any one of claims 1-8, wherein the Josephson Junction is between the first lead and the second lead.

16. A method of fabricating a quantum circuit assembly, the method comprising:

providing a first conductive layer over a substrate and a second conductive layer over the first conductive layer;

patterning the second conductive layer to define a first conductive circuit element and a second conductive circuit element;

patterning a portion of the first conductive layer exposed by patterning the second conductive layer to form a first lead connected to the first conductive layer and a second lead connected to the second conductive circuit element; and

forming a Josephson Junction having a bottom electrode connected to the first lead and a top electrode connected to the second lead.

17. The method according to claim 16, wherein patterning the portion of the first conductive layer comprises forming the first lead extending from a portion of the first conductive layer under the first conductive circuit element and forming a second lead extending from a portion of the first conductive layer under the second conductive circuit element.

18. The method according to claim 16, wherein a portion of the first conductive layer exposed by patterning the second conductive layer is a first portion, the method further comprising: covering the first lead and the second lead with an etch protective layer; and performing an etch to remove a second portion of the first conductive layer exposed by patterning the second conductive layer.

19. The method according to claim 18, further comprising continuing to perform the etch to remove a portion of the first conductive layer under the first conductive circuit element and under the second conductive circuit element.

20. The method according to claim 18, wherein performing the etch comprises performing an etch that has a higher etch rate for the first conductive layer than for the second conductive layer.

21. The method according to any one of claims 16-20, wherein forming the Josephson Junction comprises:

providing a layer of oxide over at least a portion of the first lead; and

depositing a strip of conductive material over a portion of the second lead and over the layer of oxide provided over the portion of the first lead.

22. The method according to any one of claims 16-20, wherein forming the Josephson Junction comprises forming the Josephson Junction between the first and the second leads using double-angle shadow evaporation.

23. A quantum computing device, comprising:

a quantum processing device that includes a die comprising a substrate and a plurality of qubits over or in the substrate, where at least one qubit of the plurality of qubits includes

a first conductive circuit element and a second conductive circuit element over the substrate, each having an upper portion and a lower portion, and

a Josephson Junction over the substrate and electrically connected to the first and second conductive circuit elements via a first lead and a second lead, wherein the first lead electrically connects a first electrode of the Josephson Junction to the lower portion of the first conductive circuit element, and the second lead electrically connects a second electrode of the Josephson Junction to the lower portion of the second conductive circuit element; and

a memory device configured to store data generated by the plurality of qubits during operation of the quantum processing device.

24. The quantum computing device according to claim 23, further comprising a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

25. The quantum computing device according to claims 23 or 24, wherein the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.