WHAT IS CLAIMED IS:

1. A method, comprising:

recei ving a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second cal ibrated voltage based on a base-emitter voltage of one or more npn transistors, and a stress-impaired reference voltage;

determining a set of reference values based on the first calibrated vol tage, the second calibrated voltage, and the stress-impaired reference voltage;

calculating a gain correction factor based on a function of the set of reference values and a set of temperature-dependent values;

receiving an output signal based on the stress-impaired reference voltage; and adjusting the output signal based on the gain correction factor.

2. The method of claim 1, further comprising:

calculating a temperature based on an initial gain correction value and a first reference value of the set of reference values;

calculating the set of temperature-dependent values based on the calculated temperature; and

repeating the calculation of the temperature, the set of temperature-dependent values, and the gain correction factor until the temperature and the gain correction factor converge to respective values, wherein each temperature calculation is based on a last-calculated gain correction factor.

3. The method of claim 2, further comprising:

determining the set of temperature-dependent values based on indexing a lookup table by the calculated temperature;

wherein calculating the gain correction factor comprises multiplying each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum.

4. The method of claim 1, further comprising:

receiving a first voltage that is proportional to absolute temperature (a calibrated PTAT vol tage ) based on a base-emitter voltage of one of the pnp transistors,

wherein a first reference value of the set of reference values is determined based on the first calibrated voltage and the stress-impaired reference voltage,

wherein a second reference value of the set of reference values is determined based on the second calibrated voltage and the stress-impaired reference voltage,

wherein a third reference value of the set of reference values is determined based on the calibrated PTAT voltage and the stress-impaired reference voltage.

5. The method of claim 4, wherein calculating the gain correction factor comprises:

determining the gain correction factor from one or more polynomial equations based on the set of reference values the set of temperature-dependent values, the first calibrated voltage, the second calibrated voltage, the calibrated PTAT voltage, and the stress-impaired reference voltage.

6. The method of claim 4, wherein the first calibrated voltage corresponds to a sum of the base-emitter voltage of the one or more pnp transistors and the calibrated PTAT voltage.

7. The method of claim 6, wherein the first calibrated voltage, the second calibrated voltage, and the calibrated PTAT voltage are generated by a reference circuit, the reference circuit configured to:

operate first and second pnp transistors in a matched pair configuration based on a first base current through a first base of the first pnp transistor and a second base current through a second base of the second pnp transistor, the one or more pnp transistors comprising the first and second pnp transistors; and

generate an initial proportional-to-temperature voltage (an initial PTAT voltage) at a first node of a voltage divider, connected at the first base of the first pnp transistor, based on removing a current based on the first base current from the voltage divider,

wherein the calibrated PTAT voltage is based on a function of the initial PTAT voltage.

8. The method of claim 7, wherein the removed current is based on a difference between a first voltage potential at the first base of the first pnp transistor and a second vol tage potential based on a resistor connected to a second base of the second pnp transistor.

9. The method of claim 7, wherein a multiplexer provides, to an analog-to-digital converter, an analog signal selected from the first calibrated voltage, the second calibrated voltage, the calibrated PTAT voltage, and one or more analog input signals,

wherein the analog-to-digital converter generates each respective reference value of the set of reference values based on the stress-impaired reference voltage and a selected one of the first calibrated voltage, the second calibrated voltage, and the calibrated PTAT voltage, and generates the output signal based on the stress-impaired reference voltage and the analog input signal, and

wherein a processor receives the set of reference values and the output signal from the analog-to-digital converter, calculates the gain correction factor, and adjusts the output signal based on the gain correction factor.

10. A circuit, comprising:

means for receiving a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a stress-impaired reference voltage;

means for determining a set of reference values based on the first calibrated voltage, the second calibrated voltage, and the stress-impaired reference voltage;

means for calculating a gain correction factor based on a function of the set of reference values and a set of temperature-dependent values;

means for receiving an output signal based on the stress-impaired reference voltage; and means for correcting the output signal based on the gain correction factor.

11. A system for calibrating a stress-impaired output signal, comprising:

a calibration circuit providing a first calibrated pnp voltage based on a base-emitter voltage of one or more pnp transistors and a second calibrated npn voltage based on a base-emitter voltage of one or more npn transistors;

a multiplexer connected to the calibration circuit and a sense terminal, and configured to provide an analog signal selected from a sense signal at the sense terminal, the first calibrated pnp voltage, and the second calibrated npn voltage; and

an analog-to-digital converter configured to generate a digital output signal based on the analog signal selected by the multiplexer and a stress-impaired reference voltage;

a processor, the processor configured to:

control the multiplexer to sample the first calibrated pnp voltage, the second calibrated npn voltage, and the sense signal for the analog-to-digital converter;

receive a set of reference values from the analog-to-digital converter based on the stress-impaired reference voltage and a sampling of the first calibrated pnp voltage and the second calibrated npn voltage by the multiplexer;

calcula te a gain correction factor based on a set of reference values and a set of temperature-dependent values;

adjust the digital output signal based on the gain correction factor to correct for errors introduced by the stress-impaired reference voltage.

12. The system of claim 11, wherein the processor is further configured to:

calculate a temperature based on an initial gain correction value and a first reference value of the set of reference values;

calculate the set of temperature-dependent values based on the calculated temperature; and

repeat calculations of the temperature, the set of temperature-dependent values, and the gain correction factor until the temperature and the gain correction factor converge to respective values, wherein each temperature calculation is based on a last-calculated gain correction factor.

13. The system of claim 12, wherein the processor is further configured to:

determine the set of temperature-dependent values based on indexing a lookup table by the calculated temperature;

wherein calculating the gain correction factor comprises multiplying each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum.

14. The system of claim 12, wherein the processor is further configured to:

provide an output temperature value based on a convergence of the repeated calculations of the temperature.

15. The system of claim 1 1, wherein the calibration circuit further provides a voltage that is proportional to absolute temperature (a calibrated PTAT voltage) based on the base-emitter voltage of one of the pnp transistors,

wherein a first reference value of the set of reference values is determined based on the first calibrated pnp voltage and the stress-impaired reference voltage,

wherein a second reference value of the set of reference values is determined based on the second calibrated npn voltage and the stress-impaired reference voltage, and

wherein a third reference value of the set of reference values is determined based on the calibrated PTAT voltage and the stress-impaired reference voltage.

16. The system of claim 15, wherein the gain correction factor is determined from one or more polynomial equations based on the set of reference values the set of temperature-dependent values, the first calibrated pnp voltage, the second calibrated npn voltage, the calibrated PTAT voltage, and the stress-impaired reference voltage.

17. The system of claim 16, wherein the first calibrated pnp voltage corresponds to a sum of the base-emitter vol tage of the one or more pnp transistors and the calibrated PTAT voltage.

18. The system of claim 17, wherein the calibration circuit is configured to:

operate first and second pnp transistors in a matched pair configuration based on a first base current through a first base of the first pnp transi stor and a second base current through a second base of the second pnp transistor, the one or more pnp transistors comprising the first and second pnp transistors; and

generate an initial proportional-to-temperature voltage (an initial PTAT voltage) at a first node of a voltage divider, connected at the first base of the first pnp transistor, based on removing a current based on the first base current from the voltage divider,

wherein the calibrated PTAT voltage is based on a function of the initial PTAT voltage.

19. The system of claim 18, wherein the removed current is based on a difference between a first voltage potential at the first base of the first pnp transistor and a second voltage potential based on a resistor connected to a second base of the second pnp transistor.

20. The system of claim 18, wherein the multiplexer provides an analog signal selected from a sense signal at the sense terminal, the first calibrated pnp voltage, the second calibrated npn voltage, and the calibrated PTAT voltage,

wherein the analog-to-digital converter generates each respective reference value of the set of reference values based on the stress-impaired reference voltage and a selected one of the first calibrated pnp voltage, the second calibrated npn voltage, and the calibrated PTAT voltage.