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1. (WO2019031553) CASCODE AMPLIFIER CIRCUIT
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/031553 International Application No.: PCT/JP2018/029797
Publication Date: 14.02.2019 International Filing Date: 08.08.2018
IPC:
H03F 1/22 (2006.01) ,H03F 3/195 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
08
Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
22
by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
195
in integrated circuits
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
別府 伸耕 BEPPU Nobuyasu; JP
Agent:
特許業務法人 楓国際特許事務所 KAEDE PATENT ATTORNEYS' OFFICE; 大阪府大阪市中央区農人橋1丁目4番34号 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011, JP
Priority Data:
2017-15617310.08.2017JP
Title (EN) CASCODE AMPLIFIER CIRCUIT
(FR) CIRCUIT AMPLIFICATEUR CASCODE
(JA) カスコード増幅回路
Abstract:
(EN) A cascode amplifier circuit (101) includes: a first transistor circuit (MM1) in which a signal is externally inputted into a signal input unit (Pi); a load circuit which is connected between the first transistor circuit (MM1) and a power supply line (Vdd); and a second transistor (M2) which is cascode-connected between the load circuit and the first transistor circuit (MM1). The first transistor circuit (MM1) is configured from a plurality of transistors (M11, M12, M13) which are connected in parallel, and is equipped with a bias circuit (3) for selectively supplying a bias voltage to the plurality of transistors (M11, M12, M13).
(FR) La présente invention concerne un circuit amplificateur cascode (101) comprenant : un premier circuit transistorisé (MM1) dans lequel un signal est entré extérieurement dans une unité d'entrée de signal (Pi) ; un circuit de charge connecté entre le premier circuit transistorisé (MM1) et une ligne d'alimentation (Vdd) ; et un second transistor (M2) connecté en cascade entre le circuit de charge et le premier circuit transistorisé (MM1). Le premier circuit transistorisé (MM1) est constitué d'une pluralité de transistors (M11, M12, M13) connectés en parallèle, et est équipé d'un circuit de polarisation (3) destiné à fournir sélectivement une tension de polarisation à la pluralité de transistors (M11, M12, M13).
(JA) 増幅回路(101)は、信号入力部(Pi)に外部から信号が入力される第1トランジスタ回路(MM1)と、第1トランジスタ回路(MM1)と電源ライン(Vdd)との間に接続された負荷回路と、この負荷回路と第1トランジスタ回路(MM1)との間にカスコード接続された第2トランジスタ(M2)と、を含むカスコード増幅回路である。第1トランジスタ回路(MM1)は並列接続された複数のトランジスタ(M11,M12,M13)で構成され、複数のトランジスタ(M11,M12,M13)に対して選択的にバイアス電圧を供給するバイアス回路(3)を備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)