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1. (WO2019031029) PHOTOELECTRIC CONVERSION ELEMENT PRODUCTION METHOD
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/031029 International Application No.: PCT/JP2018/020598
Publication Date: 14.02.2019 International Filing Date: 29.05.2018
IPC:
H01L 31/18 (2006.01) ,C23C 16/44 (2006.01) ,C23C 16/50 (2006.01) ,H01L 21/205 (2006.01) ,H01L 21/31 (2006.01) ,H01L 21/683 (2006.01) ,H01L 31/0747 (2012.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
18
Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
44
characterised by the method of coating
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
44
characterised by the method of coating
50
using electric discharges
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
04
adapted as conversion devices
06
characterised by at least one potential-jump barrier or surface barrier
072
the potential barriers being only of the PN heterojunction type
0745
comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
0747
comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT solar cells
Applicants:
株式会社カネカ KANEKA CORPORATION [JP/JP]; 大阪府大阪市北区中之島2-3-18 2-3-18, Nakanoshima, Kita-ku, Osaka-shi, Osaka 5308288, JP
Inventors:
福田 将典 FUKUDA, Masanori; JP
波内 俊文 NAMIUCHI, Toshifumi; JP
松田 高洋 MATSUDA, Takahiro; JP
Agent:
特許業務法人はるか国際特許事務所 HARUKA PATENT & TRADEMARK ATTORNEYS; 東京都千代田区六番町3 六番町SKビル5階 Rokubancho SK Bldg. 5th Floor, 3, Rokubancho, Chiyoda-ku, Tokyo 1020085, JP
Priority Data:
2017-15443409.08.2017JP
2017-15443509.08.2017JP
2017-15443609.08.2017JP
Title (EN) PHOTOELECTRIC CONVERSION ELEMENT PRODUCTION METHOD
(FR) PROCÉDÉ DE FABRICATION D'ÉLÉMENT DE CONVERSION PHOTOÉLECTRIQUE
(JA) 光電変換素子の製造方法
Abstract:
(EN) The present invention provides a production method for a photoelectric conversion element having a first and second main surface and including a first thin film formed on the first main surface side of the semiconductor substrate and a second thin film formed on the second main surface side of the semiconductor substrate, the method comprising a first disposition step of disposing, at a first film-forming position (81) in a first film-forming room (61), a first semiconductor substrate whereon no first thin film and no second thin film have been formed, a second disposition step of disposing, at a second film-forming position (82) in the first film-forming room (61), a second semiconductor substrate having at least a first thin film formed on the first main surface side and no second thin film formed on the second main surface side, and a first film-forming step of forming, in the first film-forming room (61) and within the same time period, the first thin film on the first main surface side of the first semiconductor substrate and the second thin film on the second main surface side of the second semiconductor substrate.
(FR) La présente invention concerne un procédé de fabrication d'un élément de conversion photoélectrique possédant une première et une seconde surface principale et comprenant un premier film mince formé du côté première surface principale du substrat semi-conducteur et un second film mince formé du côté seconde surface principale du substrat semi-conducteur, le procédé comprenant une première étape de disposition consistant à disposer, au niveau d'une première position (81) de formation de film dans une première salle (61) de formation de film, un premier substrat semi-conducteur sur lequel aucun premier film mince et aucun second film mince n'ont été formés, une seconde étape de disposition consistant à disposer, au niveau d'une seconde position (82) de formation de film dans la première salle (61) de formation de film, un second substrat semi-conducteur possédant au moins un premier film mince formé du côté première surface principale et aucun second film mince formé du côté seconde surface principale, et une première étape de formation de film consistant à former, dans la première salle (61) de formation de film et dans la même période, le premier film mince du côté première surface principale du premier substrat semi-conducteur et le second film mince du côté seconde surface principale du second substrat semi-conducteur.
(JA) 本開示の光電変換素子の製造方法は、第1、第2の主面を有し、半導体基板の第1の主面側に形成された第1の薄膜と、半導体基板の前記第2の主面側に形成された第2の薄膜と、を含む光電変換素子の製造方法であって、第1の薄膜及び第2の薄膜が形成されていない第1の半導体基板を、第1の製膜室(61)における第1の製膜位置(81)に配置する第1の配置ステップと、第1の主面側には少なくとも第1の薄膜が形成され、第2の主面側には第2の薄膜が形成されていない第2の半導体基板を、第1の製膜室(61)における第2の製膜位置(82)に配置する第2の配置ステップと、第1の製膜室(61)において、第1の半導体基板の第1の主面側には第1の薄膜を、第2の半導体基板の第2の主面側には第2の薄膜を、同一期間内に形成する第1の製膜ステップと、を含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)