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1. (WO2019030288) ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR PRODUCING SUCH AN ELECTRONIC SYSTEM
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/030288 International Application No.: PCT/EP2018/071516
Publication Date: 14.02.2019 International Filing Date: 08.08.2018
IPC:
H01L 21/60 (2006.01) ,H01L 21/683 (2006.01) ,H01L 25/10 (2006.01) ,H01L 25/065 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/498 (2006.01) ,H05K 1/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
10
the devices having separate containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Applicants:
3DIS TECHNOLOGIES [FR/FR]; 478 Rue de la Découverte 31670 LABEGE, FR
Inventors:
GHANNAM, Ayad; FR
Agent:
ARGYMA; 36 rue d'Alsace Lorraine 31000 TOULOUSE, FR
Priority Data:
175758808.08.2017FR
Title (EN) ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR PRODUCING SUCH AN ELECTRONIC SYSTEM
(FR) SYSTEME ELECTRONIQUE COMPRENANT UNE COUCHE DE REDISTRIBUTION INFERIEURE ET PROCEDE DE FABRICATION D'UN TEL SYSTEME ELECTRONIQUE
Abstract:
(EN) The invention relates to a method for producing an electronic system (S), comprising: - a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member (2) to form a lower redistribution layer (7) defining a plurality of lower connection ports (71) connected to a plurality of inner connection ports (72), - a step of depositing at least one electronic component (3) on the lower redistribution layer (7), and - a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors (30) of the electronic component (3) to the inner connection ports (72) of the lower redistribution layer (7).
(FR) Un procédé de fabrication d'un système électronique (S) comprenant: • - une étape de réalisation d'une pluralité d'interconnexions réalisées par dépôt métallique sur l'élément sacrificiel (2) afin de former une couche de redistribution inférieure (7) définissant une pluralité de ports de connexion inférieurs (71) reliée à une pluralité de ports de connexion internes (72), • - une étape de dépôt d'au moins un composant électronique (3) sur la couche de redistribution inférieure (7), et • - une étape de réalisation d'une pluralité d'interconnexions tridimensionnelles réalisées par dépôt métallique de manière à relier les connecteurs (30) du composant électronique (3) aux ports de connexion internes (72) de la couche de redistribution inférieure (7).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)