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1. (WO2019029008) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND LIQUID CRYSTAL DISPLAY PANEL
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/029008 International Application No.: PCT/CN2017/106973
Publication Date: 14.02.2019 International Filing Date: 20.10.2017
IPC:
H01L 27/13 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
13
combined with thin-film or thick-film passive components
Applicants:
武汉华星光电半导体显示技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋305室 305 Room, Building C5, Biolake of Optics Valley No. 666 Gaoxin Avenue Wuhan East Lake High-Tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
李松杉 LI, Songshan; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806, Zhongdi Building China University of Geosciences Base No. 8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201710674521.907.08.2017CN
Title (EN) THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND LIQUID CRYSTAL DISPLAY PANEL
(FR) TRANSISTOR À COUCHE MINCE ET PROCÉDÉ DE FABRICATION DE TRANSISTOR À COUCHE MINCE, ET PANNEAU D’AFFICHAGE À CRISTAUX LIQUIDES
(ZH) 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
Abstract:
(EN) The present invention relates to the technical field of displays, and provides a thin film transistor (100) and a method for manufacturing the thin film transistor (100), and a liquid crystal display panel (200). The thin film transistor (100) comprises a substrate (110), a grid layer (120), and an insulation layer (130), the grid layer (120) being formed on the substrate (110), and the insulation layer (130) covering the grid layer (120); a semiconductor layer (140), formed on the insulation layer (130); a conductor layer (150), formed on the semiconductor layer (140); an insulation spacer layer (160), formed on the insulation layer (130); a source/drain layer (170), formed on the conductor layer (150) and the insulation spacer layer (160); and a passivation layer (180), formed on the source/drain layer (170) and the semiconductor layer (140). The insulation spacer layer (160) is provided between the source/drain layer (170) and the semiconductor layer (140), thus solving the problem of overlarge leakage current of the thin film transistor (100).
(FR) La présente invention se rapporte au champ technique des afficheurs, et concerne un transistor à couche mince (100) et un procédé de fabrication du transistor à couche mince (100), et un panneau d’affichage à cristaux liquides (200). Le transistor à couche mince (100) comprend un substrat (110), une couche de grille (120), et une couche d’isolation (130), la couche de grille (120) étant formée sur le substrat (110), et la couche d’isolation (130) recouvrant la couche de grille (120) ; une couche semi-conductrice (140), formée sur la couche d’isolation (130) ; une couche conductrice (150), formée sur la couche semi-conductrice (140) ; une couche d’entretoise (160) d’isolation, formée sur la couche d’isolation (130) ; une couche de source/drain (170), formée sur la couche conductrice (150) et la couche d’entretoise (160) d’isolation ; et une couche de passivation (180), formée sur la couche de source/drain (170) et la couche semi-conductrice (140). La couche d’entretoise (160) d’isolation est disposée entre la couche de source/drain (170) et la couche semi-conductrice (140), résolvant ainsi le problème de courant de fuite excessif du transistor à couche mince (100).
(ZH) 一种薄膜晶体管(100)及薄膜晶体管(100)的制造方法、液晶显示面板(200),涉及显示技术领域。该薄膜晶体管(100)包括基板(110)、栅极层(120)及绝缘层(130),栅极层(120)形成于基板(110)上,绝缘层(130)覆盖于栅极层(120);半导体层(140),形成于绝缘层(130)上;导体层(150),形成于半导体层(140)上;绝缘间隔层(160),形成在绝缘层(130)上;源漏极层(170),形成在导体层(150)和绝缘间隔层(160)上;钝化层(180),形成于源漏极层(170)和半导体层(140)上;其中,绝缘间隔层(160)位于源漏极层(170)和半导体层(140)之间,可以解决薄膜晶体管(100)存在漏电流过大的问题。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20190043994