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1. (WO2019028972) METHOD FOR PREPARING BOTTOM-GATE LOW TEMPERATURE POLY-SILICON TRANSISTOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/028972 International Application No.: PCT/CN2017/102585
Publication Date: 14.02.2019 International Filing Date: 21.09.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants:
武汉华星光电半导体显示技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋305室 305 Room, Building C5,Biolake of Optics Valley,No.666 Gaoxin Avenue, Wuhan East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
李松杉 LI, Songshan; CN
Agent:
深圳市威世博知识产权代理事务所(普通合伙) CHINA WISPRO INTELLECTUAL PROPERTY LLP.; 中国广东省深圳市 南山区高新区粤兴三道8号中国地质大学产学研基地中地大楼A806 Room A806 Zhongdi Building, China University of Geosciences Base, No.8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201710670222.807.08.2017CN
Title (EN) METHOD FOR PREPARING BOTTOM-GATE LOW TEMPERATURE POLY-SILICON TRANSISTOR
(FR) PROCÉDÉ DE PRÉPARATION DE TRANSISTOR EN POLYSILICIUM À BASSE TEMPÉRATURE À GRILLE INFÉRIEURE
(ZH) 底栅型低温多晶硅晶体管的制备方法
Abstract:
(EN) A method for preparing a bottom-gate low temperature poly-silicon transistor, comprising: preparing a first stacked structure on a base substrate; successively preparing a poly-silicon layer and an etching barrier layer on the first stacked structure; simultaneously patterning the poly-silicon layer and the etching barrier layer, so that the etching barrier layer covers part of the poly-silicon layer; and performing ion implantation on the part of the poly-silicon layer that is not covered by the etching barrier layer to form a source/drain region of the low temperature poly-silicon transistor. The method can simplify a process flow and reduce manufacturing costs.
(FR) L'invention concerne un procédé de préparation de transistor en polysilicium à basse température à grille inférieure, consistant : à préparer une première structure empilée sur un substrat de base; à préparer successivement une couche de polysilicium et une couche de barrière de gravure sur la première structure empilée; à tracer simultanément des motifs sur la couche de polysilicium et la couche de barrière de gravure, de sorte que la couche de barrière de gravure recouvre une partie de la couche de polysilicium; et à procéder à une implantation d'ions sur la partie de la couche de polysilicium qui n'est pas recouverte par la couche de barrière de gravure pour former une zone de source/drain du transistor en polysilicium à basse température. Le procédé peut simplifier un flux de processus et réduire des coûts de fabrication.
(ZH) 一种底栅型低温多晶硅晶体管的制备方法,包括:在衬底基板上制备第一层叠结构;依次在第一层叠结构上制备多晶硅层以及蚀刻阻挡层;同时对多晶硅层及蚀刻阻挡层进行图形化处理,以使得蚀刻阻挡层覆盖部分多晶硅层;在未被蚀刻阻挡层覆盖的多晶硅层上进行离子注入,以形成低温多晶硅晶体管的源极/漏极区域。能够简化工艺流程,节省制造成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20190123173