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1. (WO2019028934) LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND PREPARATION METHOD THEREFOR
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/028934 International Application No.: PCT/CN2017/098337
Publication Date: 14.02.2019 International Filing Date: 21.08.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley No.666 Gaoxin Avenue, East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
肖东辉 XIAO, Donghui; CN
Agent:
深圳市铭粤知识产权代理有限公司 MING & YUE INTELLECTUAL PROPERTY LAW FIRM; 中国广东省深圳市 南山区南山街道前海路泛海城市广场2栋604室 Room 604 Building 2, Oceanwide City Square, Qianhai Road, Nanshan Street, Nanshan District Shenzhen, Guangdong 518066, CN
Priority Data:
201710668038.X07.08.2017CN
Title (EN) LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND PREPARATION METHOD THEREFOR
(FR) TRANSISTOR À COUCHES MINCES DE POLYSILICIUM BASSE TEMPÉRATURE ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 低温多晶硅薄膜晶体管及其制备方法
Abstract:
(EN) A preparation method for a low temperature polysilicon thin film transistor, comprising steps of: sequentially forming a polysilicon active layer (2) and a gate insulation layer (3) covering the polysilicon active layer (2) on a base substrate (1); using an ion implantation process to implant nitrogen ions to the surface of the polysilicon active layer (2) facing towards the gate insulation layer (3), so as to form an ion implantation layer (6a); and using a high temperature annealing process to recrystallize the ion implantation layer (6a), so as to form a silicon nitride spacer layer (6) between the polysilicon active layer (2) and the gate insulation layer (3). A low temperature crystalline silicon thin film transistor, comprising a polysilicon active layer (2), a gate insulation layer (3), a gate electrode (4), a source electrode (5a), and a drain electrode (5b) which are successively provided on a base substrate (1), a silicon nitride spacer layer (6) being formed on a joint interface between the polysilicon active layer (2) and the gate insulation layer (3), the silicon nitride spacer layer (6) and the polysilicon active layer (2) being of an integrated interconnected structure.
(FR) L'invention concerne un procédé de préparation d'un transistor à couches minces de polysilicium basse température comprenant les étapes consistant à : former séquentiellement une couche active de polysilicium (2) et une couche d'isolation de grille (3) recouvrant la couche active de polysilicium (2) sur un substrat de base (1) ; utiliser un procédé d'implantation ionique pour implanter des ions azote sur la surface de la couche active de polysilicium (2) tournée vers la couche d'isolation de grille (3), de manière à former une couche d'implantation ionique (6a) ; et utiliser un processus de recuit à haute température pour recristalliser la couche d'implantation ionique (6a), de manière à former une couche d'espacement de nitrure de silicium (6) entre la couche active de polysilicium (2) et la couche d'isolation de grille (3). Un transistor à couches minces de silicium cristallin basse température, comprenant une couche active de polysilicium (2), une couche d'isolation de grille (3), une électrode de grille (4), une électrode de source (5a) et une électrode de drain (5b) qui sont disposées successivement sur un substrat de base (1), une couche d'espacement de nitrure de silicium (6) étant formée sur une interface de jonction entre la couche active de polysilicium (2) et la couche d'isolation de grille (3), la couche d'espacement de nitrure de silicium (6) et la couche active de polysilicium (2) étant d'une structure interconnectée intégrée.
(ZH) 一种低温多晶硅薄膜晶体管的制备方法,其包括:在衬底基板(1)上依次制备形成多晶硅有源层(2)和覆盖该多晶硅有源层(2)的栅极绝缘层(3);应用离子植入工艺,在该多晶硅有源层(2)的朝向该栅极绝缘层(3)的表面上注入氮离子,形成离子注入层(6a);应用高温退火工艺,使该离子注入层(6a)重结晶,在该多晶硅有源层(2)和该栅极绝缘层(3)之间形成氮化硅间隔层(6)。一种低温晶硅薄膜晶体管,包括依次设置在衬底基板(1)上的多晶硅有源层(2)、栅极绝缘层(3)、栅电极(4)、源电极(5a)和漏电极(5b),其中,该多晶硅有源层(2)和该栅极绝缘层(3)之间的连接界面形成有氮化硅间隔层(6),该氮化硅间隔层(6)与该多晶硅有源层(2)是一体相互连接的结构。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)