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1. (WO2019028314) HIGH DENSITY PIXELATED-LED CHIPS AND CHIP ARRAY DEVICES, AND FABRICATION METHODS
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Pub. No.: WO/2019/028314 International Application No.: PCT/US2018/045102
Publication Date: 07.02.2019 International Filing Date: 03.08.2018
IPC:
H01L 27/15 (2006.01) ,H01L 33/54 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
15
including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
52
Encapsulations
54
having a particular shape
Applicants:
CREE, INC. [US/US]; 4600 Silicon Drive Durham, North Carolina 27703, US
Inventors:
ANDREWS, Peter; US
Agent:
GUSTAFSON, Vincent, K.; US
Priority Data:
62/541,03303.08.2017US
62/655,29610.04.2018US
62/655,30310.04.2018US
Title (EN) HIGH DENSITY PIXELATED-LED CHIPS AND CHIP ARRAY DEVICES, AND FABRICATION METHODS
(FR) PUCES DEL PIXELISÉES À HAUTE DENSITÉ ET DISPOSITIFS À RÉSEAU DE PUCES, ET PROCÉDÉS DE FABRICATION
Abstract:
(EN) Pixelated-LED chips and related methods are disclosed. A pixelated-LED chip includes an active layer with independently electrically accessible active layer portions arranged on or over a light-transmissive substrate. The active layer portions are configured to illuminate different light-transmissive substrate portions to form pixels. Various enhancements may beneficially provide increased contrast (i.e., reduced cross-talk between pixels) and/or promote inter-pixel illumination homogeneity, without unduly restricting light utilization efficiency. In some aspects, a light extraction surface of each substrate portion includes protruding features and light extraction surface recesses. Lateral borders between different pixels are aligned with selected light extraction surface recesses. In some aspects, selected light extraction surface recesses extend through an entire thickness of the substrate. Other technical benefits may additionally or alternatively be achieved.
(FR) La présente invention concerne des puces DEL pixelisées et des procédés associés. Une puce DEL pixelisée comprend une couche active avec des parties de couche active accessibles électriquement de manière indépendante disposées sur ou au dessus d'un substrat transmettant la lumière. Les parties de couche active sont conçues pour éclairer différentes parties du substrat transmettant la lumière pour former des pixels. Diverses améliorations peuvent avantageusement fournir un contraste accru (à savoir une diaphonie réduite entre pixels) et/ou favoriser une homogénéité d'éclairage entre pixels, sans restreindre indûment l'efficacité d'utilisation de la lumière. Selon certains aspects, une surface d'extraction de lumière de chaque partie du substrat comprend des éléments saillants et des évidements de surface d'extraction de lumière. Des bordures latérales entre différents pixels sont alignées avec des évidements de surface d'extraction de lumière sélectionnés. Selon certains aspects, les évidements de surface d'extraction de lumière sélectionnés s'étendent sur toute l'épaisseur du substrat. D'autres avantages techniques peuvent en outre ou en variante être obtenus.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)