Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019028136) SELECTIVE DEPOSITION OF SIN ON HORIZONTAL SURFACES
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/028136 International Application No.: PCT/US2018/044800
Publication Date: 07.02.2019 International Filing Date: 01.08.2018
IPC:
H01L 21/02 (2006.01) ,H01L 27/11524 (2017.01) ,H01L 21/3213 (2006.01) ,H01L 21/027 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
Applicants:
LAM RESEARCH CORPORATION [US/US]; 4650 Cushing Parkway Fremont, California 94538, US
Inventors:
VAN SCHRAVENDIJK, Bart J.; US
GUPTA, Awnish; US
VAN CLEEMPUT, Patrick A.; US
PARK, Jason Daejin; US
Agent:
BERGIN, Denise S.; US
AUSTIN, James E.; US
SAMPSON, Roger S.; US
VILLENEUVE, Joseph M.; US
WEAVER, Jeffrey K.; US
Priority Data:
62/541,26204.08.2017US
Title (EN) SELECTIVE DEPOSITION OF SIN ON HORIZONTAL SURFACES
(FR) DÉPÔT SÉLECTIF DE NITRURE DE SILICIUM SUR DES SURFACES HORIZONTALES
Abstract:
(EN) Methods and apparatuses for selectively depositing silicon nitride (SiN) via high-density plasma chemical vapor deposition (HDP CVD) to form a SiN pad on an exposed flat surface of a nitride layer in a 3D NAND staircase structure with alternating oxide and nitride layers are provided. In some embodiments, selective etching is performed to remove undesirable buildup of SiN on sidewalls of the oxide layers of the staircase structure. Nitride layers of the staircase structure are replaced with tungsten (W) to form tungsten wordlines, while the SiN pads are replaced with tungsten to from landing pads, which prevent punchthrough of the tungsten wordlines on the staircase structure by interconnects extending thereto.
(FR) Cette invention concerne des procédés et des appareils de dépôt sélectif de nitrure de silicium (SiN) par dépôt chimique en phase vapeur assisté par plasma haute densité (HDP CVD) pour former une pastille de SiN sur une surface plane exposée d'une couche de nitrure dans une structure en escalier NON-ET 3D avec des couches d'oxyde et de nitrure alternées. Selon certains modes de réalisation, une gravure sélective est effectuée pour éliminer l'accumulation indésirable de SiN sur les parois latérales des couches d'oxyde de la structure en escalier. Des couches de nitrure de la structure en escalier sont remplacées par du tungstène (W) pour former des lignes de mots de tungstène, tandis que les pastilles de SiN sont remplacées par du tungstène pour former des plages d'accueil, qui empêchent le perçage des lignes de mots de tungstène sur la structure en escalier par des interconnexions s'étendant jusqu'à celles-ci.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)