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1. (WO2019028074) WIRING WITH EXTERNAL TERMINAL
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Pub. No.: WO/2019/028074 International Application No.: PCT/US2018/044695
Publication Date: 07.02.2019 International Filing Date: 31.07.2018
IPC:
H01L 21/768 (2006.01) ,H01L 27/06 (2006.01) ,H01L 27/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, Idaho 83716-9632, US
Inventors:
SATO, Toshiyuki; JP
Agent:
ITO, Mika; US
ANDKEN, Kerry Lee; US
ENG, Kimton; US
FAUTH D., Justen; US
ITO, Mika; US
HEGSTROM, Brandon; US
MA, Yue Matthew; US
QUECAN, Andrew F.; US
STERN, Ronald; US
MEIKLEJOHN, Paul T.; US
SPAITH, Jennifer; US
ORME, Nathan; US
CORDRAY, Michael S.; US
Priority Data:
15/669,80104.08.2017US
Title (EN) WIRING WITH EXTERNAL TERMINAL
(FR) CÂBLAGE À BORNE EXTERNE
Abstract:
(EN) Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad included in a pad formation area that receives a power voltage; a sub-threshold current reduction circuit (SCRC) included in a peripheral circuit area including a via disposed on a first side of the peripheral circuit area, and a wiring that couples the pad to the via. The SCRC further includes: a voltage line coupled to the via; a logic gate circuit that propagates a signal; an SCRC voltage line coupled to the logic gate circuit; and a SCRC switch disposed in proximity to the via and couples the SCRC voltage line to the voltage line.
(FR) L’invention concerne des appareils d’application de bornes externes d’un dispositif à semi-conducteur. Un appareil donné à titre d'exemple comprend : une pastille incluse dans une zone de formation de pastille qui reçoit une tension de puissance ; un circuit de réduction de courant inférieur au seuil (SCRC) inclus dans une zone de circuit périphérique comprenant un trou d'interconnexion disposé sur un premier côté de la zone de circuit périphérique, et un câblage qui couple la pastille au trou d'interconnexion. Le SCRC comprend en outre : une ligne de tension couplée au trou d'interconnexion ; un circuit de porte logique qui propage un signal ; une ligne de tension SCRC couplée au circuit de porte logique ; et un commutateur SCRC disposé à proximité du trou d'interconnexion et couplant la ligne de tension SCRC à la ligne de tension.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)