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1. (WO2019028072) VERTICAL LAYERED FINITE ALPHABET ITERATIVE DECODING
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Pub. No.: WO/2019/028072 International Application No.: PCT/US2018/044691
Publication Date: 07.02.2019 International Filing Date: 31.07.2018
IPC:
H03M 13/03 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
13
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
Applicants:
CODELUCIDA, INC. [US/US]; 100 N. Stone Avenue, Suite 1103 Tucson, Arizona 85701, US
Inventors:
REYNWAR, Benedict J.; US
PLANJERY, Shiva Kumar; US
DECLERCQ, David; US
Agent:
GOTTLIEB, Kirk A.; US
Priority Data:
16/049,72430.07.2018US
62/539,47631.07.2017US
Title (EN) VERTICAL LAYERED FINITE ALPHABET ITERATIVE DECODING
(FR) DÉCODAGE ITÉRATIF À ALPHABET FINI À COUCHES VERTICALES
Abstract:
(EN) This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.
(FR) La présente invention concerne un procédé et un appareil de décodage itératif à alphabet fini à couches verticales de codes de contrôle de parité à faible densité (LDPC) qui sont mis en œuvre sur des matrices de contrôle de parité consistant en des blocs de sous-matrices. Le décodage itératif consiste à passer des messages entre des nœuds variables et des nœuds de contrôle du graphe de Tanner qui, associés à une ou plusieurs sous-matrices, constituent des blocs de décodage, les messages relevant d'un alphabet fini. Divers modes de réalisation du procédé et de l'appareil de l'invention permettent d'obtenir des débits très élevés au moyen d'une consommation de ressources matérielles et d'une puissance faibles.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)