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1. (WO2019027981) DUAL PHASED ARRAY WITH SINGLE POLARITY BEAM STEERING INTEGRATED CIRCUITS
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Pub. No.: WO/2019/027981 International Application No.: PCT/US2018/044545
Publication Date: 07.02.2019 International Filing Date: 31.07.2018
IPC:
H01Q 21/06 (2006.01) ,H01Q 21/24 (2006.01) ,H01Q 23/00 (2006.01) ,H01Q 25/00 (2006.01) ,H04B 7/06 (2006.01) ,H04W 16/28 (2009.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
21
Aerial arrays or systems
06
Arrays of individually energised aerial units similarly polarised and spaced apart
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
21
Aerial arrays or systems
24
Combinations of aerial units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
23
Aerials with active circuits or circuit elements integrated within them or attached to them
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
25
Aerials or aerial systems providing at least two radiating patterns
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
B
TRANSMISSION
7
Radio transmission systems, i.e. using radiation field
02
Diversity systems
04
using a plurality of spaced independent aerials
06
at transmitting station
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
W
WIRELESS COMMUNICATION NETWORKS
16
Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cell structures
24
Cell structures
28
using beam steering
Applicants:
ANOKIWAVE, INC. [US/US]; 11236 El Camino Real Suite 100 San Diego, CA 92130, US
Inventors:
MCMORROW, Robert; US
GRESHAM, Robert, Ian; US
Agent:
SAUNDERS, Steven G.; US
ASHER, Robert, M.; US
SUNSTEIN, Bruce, D.; US
SAUNDERS, Steven, G.; US
MURPHY, Timothy, M.; US
Priority Data:
15/669,57504.08.2017US
Title (EN) DUAL PHASED ARRAY WITH SINGLE POLARITY BEAM STEERING INTEGRATED CIRCUITS
(FR) RÉSEAU À COMMANDE DE PHASE DOUBLE AVEC CIRCUITS INTÉGRÉS DE DIRECTION À FAISCEAU DE POLARITÉ UNIQUE
Abstract:
(EN) A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).
(FR) L'invention concerne un réseau à commande de phase comprenant un substrat laminaire, une pluralité d'éléments sur le substrat laminaire formant un réseau à commande de phase patch, et des premier et second ensembles de circuits intégrés sur le substrat laminaire. Le premier ensemble de circuits intégrés, dont chacun est des circuits intégrés à polarité unique, se connecte à un premier ensemble de la pluralité d'éléments, et sont configurés pour fonctionner à l'aide de premiers signaux ayant une première polarité. De manière similaire, chaque circuit intégré du second ensemble de circuits intégrés est également un circuit intégré à polarité unique et se connecte à un second ensemble de la pluralité d'éléments. En outre, chacun du second ensemble de circuits intégrés est configuré pour fonctionner à l'aide de seconds signaux ayant une seconde polarité. La première polarité est sensiblement orthogonale à la seconde polarité (c'est-à-dire ne pas interférer l'une avec l'autre).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)