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1. (WO2019027868) METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A BURIED INSULATING LAYER FORMED BY ANNEALING A SUPERLATTICE
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Pub. No.: WO/2019/027868 International Application No.: PCT/US2018/044305
Publication Date: 07.02.2019 International Filing Date: 30.07.2018
Chapter 2 Demand Filed: 29.01.2019
IPC:
H01L 29/15 (2006.01) ,H01L 21/324 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
15
Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Applicants:
ATOMERA INCORPORATED [US/US]; 750 University Avenue, Suite 280 Los Gatos, California 95032, US
Inventors:
MEARS, Robert J.; US
STEPHENSON, Robert, John; GB
WEEKS, Keith, Doran; US
CODY, Nyles, Wynn; US
HYTHA, Marek; US
Agent:
REGAN, Christopher, F.; US
WARTHER, Richard K.; US
WOODSON, II, John F.; US
TAYLOR, Michael W.; US
ABID, Jack G.; US
CARUS, David S.; US
MCKINNEY, Matthew G.; US
Priority Data:
15/664,02831.07.2017US
Title (EN) METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A BURIED INSULATING LAYER FORMED BY ANNEALING A SUPERLATTICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR AVEC UNE COUCHE ISOLANTE ENTERRÉE FORMÉE PAR RECUIT D'UN SUPER-RÉSEAU
Abstract:
(EN) A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.
(FR) Un procédé de fabrication d'un dispositif à semi-conducteur peut consister à former un super-réseau sur un substrat semi-conducteur comprenant une pluralité respective de groupes de couches empilés. Chaque groupe de couches peut comprendre une pluralité de monocouches semi-conductrices de base empilées définissant une partie semi-conductrice de base, et au moins une monocouche non semi-conductrice contrainte à l'intérieur d'un réseau cristallin de parties semi-conductrices de base adjacentes. En outre, au moins certains atomes semi-conducteurs provenant de parties semi-conductrices de base opposées peuvent être chimiquement liés ensemble au moyen de la ou des monocouches non semi-conductrices situées entre eux. Le procédé peut en outre consister à former de façon épitaxiale une couche semi-conductrice sur le super-réseau, et à recuire le super-réseau pour former une couche isolante enterrée dans laquelle au moins certains atomes semi-conducteurs ne sont plus liés chimiquement ensemble au moyen de la ou des monocouches non-conductrices situées entre eux.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)