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1. (WO2019027811) HIGH ASPECT RATIO SELECTIVE LATERAL ETCH USING CYCLIC PASSIVATION AND ETCHING
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Pub. No.: WO/2019/027811 International Application No.: PCT/US2018/043967
Publication Date: 07.02.2019 International Filing Date: 26.07.2018
IPC:
H01L 21/3065 (2006.01) ,H01L 21/3213 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/67 (2006.01) ,H05H 1/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H
PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY- CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
1
Generating plasma; Handling plasma
24
Generating plasma
46
using applied electromagnetic fields, e.g. high frequency or microwave energy
Applicants:
LAM RESEARCH CORPORATION [US/US]; 4650 Cushing Parkway Fremont, California 94538, US
Inventors:
EASON, Kwame; US
PARK, Pilyeon; US
KAWAGUCHI, Mark Naoshi; US
PARK, Seung-Ho; US
CHANG, Hsiao-Wei; US
Agent:
KESICH, Amanda M.; US
WEAVER, Jeffrey K.; US
AUSTIN, James E.; US
VILLENEUVE, Joseph M.; US
SAMPSON, Roger S.; US
GRIFFITH, John F.; US
BERGIN, Denise S.; US
SCHOLZ, Christian D.; US
Priority Data:
15/667,55102.08.2017US
Title (EN) HIGH ASPECT RATIO SELECTIVE LATERAL ETCH USING CYCLIC PASSIVATION AND ETCHING
(FR) GRAVURE LATÉRALE SÉLECTIVE À RAPPORT D'ASPECT ÉLEVÉ UTILISANT UNE PASSIVATION CYCLIQUE ET UNE GRAVURE CYCLIQUE
Abstract:
(EN) Methods and apparatus for laterally etching unwanted material from the sidewalls of a recessed feature are described herein. In various embodiments, the method involves etching a portion of the sidewalls, depositing a protective film over a portion of the sidewalls, and cycling the etching and deposition operations until the unwanted material is removed from the entire depth of the recessed feature. Each etching and deposition operation may target a particular depth along the sidewalls of the feature. In some cases, the unwanted material is removed from the bottom of the feature up, and in other cases the unwanted material is removed from the top of the feature down. Some combination of these may also be used.
(FR) L'invention concerne des procédés et un appareil permettant de graver latéralement un matériau indésirable à partir des parois latérales d'un élément évidé. Dans divers modes de réalisation, le procédé comprend la gravure d'une partie des parois latérales, le dépôt d'un film protecteur sur une partie des parois latérales, et la répétition des opérations de gravure et de dépôt jusqu'à ce que le matériau indésirable soit retiré de toute la profondeur de l'élément évidé. Chaque opération de gravure et de dépôt peut cibler une profondeur particulière le long des parois latérales de l'élément. Dans certains cas, le matériau indésirable est retiré de l'élément du bas vers le haut et, dans d'autres cas, le matériau indésirable est retiré de l'élément du haut vers le bas. Certaines combinaisons de ces retraits peuvent également être utilisées.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)