Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019027764) ELECTRONICS PACKAGE INCLUDING INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELD AND METHOD OF MANUFACTURING THEREOF
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/027764 International Application No.: PCT/US2018/043695
Publication Date: 07.02.2019 International Filing Date: 25.07.2018
IPC:
H01L 23/552 (2006.01) ,H01L 23/31 (2006.01) ,H01L 23/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
552
Protection against radiation, e.g. light
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
04
characterised by the shape
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
KAPUSTA, Christopher James; US
FILLION, Raymond Albert; US
TUOMINEN, Risto Ilkka Sakari; JP
NAGARKAR, Kaustubh, Ravindra; US
Agent:
DIMAURO, Peter, T.; US
ZHANG, Douglas, D.; US
KRAMER, John, A.; US
MIDGLEY, Stephen, G.; US
WINTER, Catherine, J.; US
Priority Data:
15/668,55303.08.2017US
Title (EN) ELECTRONICS PACKAGE INCLUDING INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELD AND METHOD OF MANUFACTURING THEREOF
(FR) BOÎTIER ÉLECTRONIQUE COMPRENANT UN BLINDAGE CONTRE LES INTERFÉRENCES ÉLECTROMAGNÉTIQUES INTÉGRÉ ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.
(FR) Un boîtier électronique comprend un substrat de support, un composant électrique ayant une première surface couplée à une première surface du substrat de support, et une structure isolante couplée à la première surface du substrat de support et des parois latérales du composant électrique. La structure isolante a une surface extérieure inclinée. Une couche conductrice encapsule le composant électrique et la surface extérieure inclinée de la structure isolante. Une première couche de câblage est formée sur une seconde surface du substrat de support. La première couche de câblage est couplée à la couche conductrice par au moins un trou d'interconnexion dans le substrat de support.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)