Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019027738) IMPROVED METAL CONTACT LANDING STRUCTURE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/027738 International Application No.: PCT/US2018/043496
Publication Date: 07.02.2019 International Filing Date: 24.07.2018
IPC:
H01L 21/3065 (2006.01) ,H01L 21/3213 (2006.01) ,H01L 21/67 (2006.01) ,H05H 1/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
H
PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY- CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
1
Generating plasma; Handling plasma
24
Generating plasma
46
using applied electromagnetic fields, e.g. high frequency or microwave energy
Applicants:
MICROMATERIALS LLC [US/US]; 2711 Centerville Road Suite 400 Wilmington, Delaware 19808, US
Inventors:
KANG, Sung Kwan; US
KIM, Kyung-Ha; US
LEE, Gill; US
Agent:
MCCORMICK, Daniel K.; US
BERNARD, Eugene J.; US
Priority Data:
62/541,38404.08.2017US
Title (EN) IMPROVED METAL CONTACT LANDING STRUCTURE
(FR) STRUCTURE D'ATTERRISSAGE DE CONTACT MÉTALLIQUE AMÉLIORÉE
Abstract:
(EN) Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively cleaning exposed nitride materials with the effluents of the plasma. The methods may also include subsequently depositing a cap material over the cleaned nitride material. The cap material may be selectively deposited on the nitride material relative to exposed regions of a dielectric material.
(FR) L'invention concerne des procédés de traitement pouvant être mis en œuvre pour former des structures semi-conductrices qui peuvent comprendre des structures de mémoire tridimensionnelles. Les procédés peuvent comprendre la formation d'un plasma d'un précurseur contenant du fluor dans une région de plasma distant d'une chambre de traitement. Les procédés peuvent comprendre en outre la mise en contact d'un substrat semi-conducteur avec des effluents du plasma. Le substrat semi-conducteur peut être logé dans une zone de traitement de la chambre de traitement. Les procédés peuvent comprendre le nettoyage sélectif de matériaux nitrure apparents avec les effluents du plasma. Les procédés peuvent également comprendre le dépôt ultérieur d'un matériau superficiel au-dessus du matériau nitrure nettoyé. Le matériau superficiel peut être déposé sélectivement sur le matériau nitrure par rapport à des régions apparentes d'un matériau diélectrique.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)