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1. (WO2019027699) ELECTRONICS PACKAGE INCLUDING INTEGRATED STRUCTURE WITH BACKSIDE FUNCTIONALITY AND METHOD OF MANUFACTURING THEREOF
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Pub. No.: WO/2019/027699 International Application No.: PCT/US2018/043060
Publication Date: 07.02.2019 International Filing Date: 20.07.2018
IPC:
H01L 23/13 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/29 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
13
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
KAPUSTA, Christopher, James; US
TUOMINEN, Risto, Iikka; JP
NAGARKAR, Kaustubh, Ravindra; US
FILLION, Raymond, Albert; US
Agent:
DIMAURO, Peter, T.; US
KRAMER, John, A.; US
WINTER, Catherine; US
ZHANG, Douglas, D.; US
MIDGLEY, Stephen, G.; US
Priority Data:
15/668,52203.08.2017US
Title (EN) ELECTRONICS PACKAGE INCLUDING INTEGRATED STRUCTURE WITH BACKSIDE FUNCTIONALITY AND METHOD OF MANUFACTURING THEREOF
(FR) BOÎTIER ÉLECTRONIQUE COMPRENANT UNE STRUCTURE INTÉGRÉE À FONCTIONNALITÉ ARRIÈRE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An electronics package includes a support substrate, an electrical component having an active surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and at least one sidewall of the electrical component. A functional layer comprising at least one functional component is formed on at least one of a sloped sidewall of the insulating structure and a backside surface of the electrical component. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is electrically coupled to the functional layer through at least one via in the support substrate.
(FR) L'invention concerne un boîtier électronique comprenant un substrat de support, un composant électrique ayant une surface active couplée à une première surface du substrat de support, et une structure isolante couplée à la première surface du substrat de support et au moins une paroi latérale du composant électrique. Une couche fonctionnelle comprenant au moins un composant fonctionnel est formée sur au moins une paroi latérale inclinée de la structure isolante et une surface arrière du composant électrique. Une première couche de câblage est formée sur une seconde surface du substrat de support. La première couche de câblage est électriquement couplée à la couche fonctionnelle par l'intermédiaire d'au moins un trou d'interconnexion dans le substrat de support.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)