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1. (WO2019027695) ELECTRONICS PACKAGE WITH INTEGRATED INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THEREOF
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Pub. No.: WO/2019/027695 International Application No.: PCT/US2018/043003
Publication Date: 07.02.2019 International Filing Date: 20.07.2018
IPC:
H01L 23/00 (2006.01) ,H01L 23/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
KAPUSTA, Christopher James; US
FILLION, Raymond Albert; US
TUOMINEN, Risto Ilkka Sakari; JP
NAGARKAR, Kaustubh Ravindra; US
Agent:
DIMAURO, Peter T.; US
ZHANG, Douglas, D.; US
WINTER, Catherine, J.; US
KRAMER, John, J.; US
MIDGLEY, Stephen, G.; US
Priority Data:
15/668,50203.08.2017US
Title (EN) ELECTRONICS PACKAGE WITH INTEGRATED INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THEREOF
(FR) BOÎTIER ÉLECTRONIQUE AVEC STRUCTURE D'INTERCONNEXION INTÉGRÉE ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.
(FR) L'invention concerne un boîtier électronique comprenant un substrat isolant, un composant électrique ayant une surface active couplée à une première surface du substrat isolant, et une structure isolante disposée de manière adjacente au composant électrique sur la première surface du substrat isolant. Une première couche de câblage est formée sur une surface supérieure de la structure isolante et s'étend le long d'au moins une surface latérale inclinée de la structure isolante. Une seconde couche de câblage est formée sur une seconde surface du substrat isolant. La seconde couche de câblage s'étend à travers une pluralité de trous d'interconnexion dans le substrat isolant pour coupler électriquement au moins un plot de contact sur la surface active du composant électrique à la première couche de câblage.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)