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1. (WO2019027627) CELL ARCHITECTURE WITH INTRINSIC DECOUPLING CAPACITOR
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Pub. No.: WO/2019/027627 International Application No.: PCT/US2018/041315
Publication Date: 07.02.2019 International Filing Date: 09.07.2018
IPC:
H01L 27/02 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/118 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
118
Masterslice integrated circuits
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTEN: International IP Administration 5775 Morehouse Drive San Diego, California, US 92121-1714, US
Inventors:
CHINTARLAPALLI REDDY, Harikrishna; US
HOLLAND, Jonathan; US
MOHAMAD, Sajin; US
Agent:
HODGES, Jonas J.; US
GELFOUND, Craig A.; US
BINDSEIL, James; US
Priority Data:
15/667,57602.08.2017US
Title (EN) CELL ARCHITECTURE WITH INTRINSIC DECOUPLING CAPACITOR
(FR) ARCHITECTURE DE CELLULES À CONDENSATEUR DE DÉCOUPLAGE INTRINSÈQUE
Abstract:
(EN) An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
(FR) L'invention concerne un circuit intégré comprenant un réseau de cellules et un premier ensemble de cellules d'embout. Le réseau de cellules comprend un premier ensemble de Mx interconnexions de puissance de couche couplé à une première tension, un premier ensemble de Mx interconnexions de couche, un second ensemble de Mx interconnexions de puissance de couche couplé à une seconde source de tension, et un second ensemble de Mx interconnexions de couche. Le premier ensemble de cellules d'embout comprend des premier et second ensembles de Mx+1 interconnexions de couche. Le premier ensemble de Mx+1 interconnexions de couche est couplé au premier ensemble de Mx interconnexions de puissance de couche et au second ensemble de Mx interconnexions de couche de façon à fournir un premier ensemble de condensateurs de découplage. Le second ensemble de Mx+1 interconnexions de couche est couplé au second ensemble de Mx interconnexions de puissance de couche et au premier ensemble de Mx interconnexions de couche de façon à fournir un second ensemble de condensateurs de découplage.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)