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1. (WO2019027599) POWER NOISE INJECTION TO CONTROL RATE OF CHANGE OF CURRENT
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CLAIMS

We claim:

1. An apparatus comprising:

a component;

a voltage generator to supply load current to the component;

first one or more circuitries to predict that the load current is to increase from a first time; and

second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.

2. The apparatus of claim 1, wherein the time period occurs immediate prior to the first time.

3. The apparatus of claim 1, wherein the first instructions are to generate useless results from the component.

4. The apparatus of any of claims 1-3, wherein the component is to execute second instructions from the first time.

5. The apparatus of claim 4, further comprising:

a multiplexer to receive the first instructions and the second instructions,

wherein the second one or more circuitries are to cause the multiplexer to output the first instructions during the time period, in anticipation of the increase in the load current from the first time.

6. The apparatus of claim 5, wherein the second one or more circuitries are to cause the multiplexer to output the second instructions subsequent to the first time.

7. The apparatus of claim 5, wherein the second one or more circuitries comprises:

a controller to receive the prediction from the first one or more circuitries, and to generate an injection status signal; and

a logical AND gate to receive the injection status signal and a load status signal, and to output a control signal, wherein the load status signal is to provide an indication of whether the component is executing as assigned workload,

wherein the control signal is to control the multiplexer to selectively output one of the first instructions or the second instructions.

8. The apparatus of any of claims 1-3, wherein:

the component is to operate in a stall condition prior to the first time; and

the component is to exit the stall condition from the first time.

9. The apparatus of any of claims 1-3, wherein:

the component is to enter in a stall condition at a second time that occurs subsequent to the first time; and

the second one or more circuitries are to, in anticipation of the component exiting from the stall condition subsequent to the second time, cause the component to execute the first instructions during another time period that occurs subsequent to the second time.

10. The apparatus of any of claims 1-3, wherein:

the component comprises a plurality of arithmetic logical units (ALUs),

wherein the second one or more circuitries are to cause one or more of the plurality of ALUs, but not all the ALUs, to execute the first instructions during the time period.

11. A system comprising:

a memory;

a processing core coupled to the memory;

a power source to supply load current to the processing core, wherein the processing core is to exit from a stall condition at a first time; and

one or more circuitries to cause an increase in the load current prior to the first time, based on the exit of the processing core from the stall condition at the first time.

12. The system of claim 11, wherein the one or more circuitries are to cause the increase in the load current immediately prior to the first time.

13. The system of claim 11, wherein the one or more circuitries are to cause the increase in the load current by causing the processing core to execute first instructions prior to the first time.

14. The system of claim 11, wherein the first instructions are not associated with an intended workload of the processing core.

15. The system of any of claims 11-14, further comprising:

an instruction pipeline to store instructions that the processing core is to execute; and another one or more circuitries to monitor for presence of one or more high power instructions in the instruction pipeline, and to predict that the processing core is to potentially and imminently exit from the stall condition current.

16. The system of claim 15, wherein:

while the processing core is to enter another stall condition and while the instruction pipeline stores another one or more high power instructions, the one or more circuitries are to cause the processing core to execute dummy instructions upon the processing core entering the another stall condition.

17. A non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to perform operations comprising:

determine that an instruction pipeline comprises a plurality of instructions to be executed by a component;

predict a first time at which the component is to start executing the plurality of instructions; and

facilitate, immediate prior to the first time, an increase in a load current supplied by a voltage regulator to the component.

18. The non-transitory computer-readable storage media of claim 17, wherein the plurality of instructions included in the pipeline is a first plurality of instructions, and wherein to facilitate the increase in the load current, the instructions cause the processor to perform operations comprising:

facilitate the component to execute a second plurality of instructions that are not included in the instruction pipeline.

19. The non-transitory computer-readable storage media of claim 18, wherein the second plurality of instructions are dummy instructions that are to generate useless results from the component.

20. The non-transitory computer-readable storage media of claim 18, wherein the

instructions, when executed, further cause the processor to:

refrain from facilitating the component to execute the second plurality of instructions, once the component starts executing the first plurality of instructions.

21. The non-transitory computer-readable storage media of any of claims 17-19, wherein to facilitate the increase in the load current, the instructions cause the processor to perform operations comprising:

inject power noise to the component.

22. A method comprising:

determining that an instruction pipeline comprises a plurality of instructions to be executed by a component;

predicting a first time at which the component is to start executing the plurality of instructions; and

facilitating, immediate prior to the first time, an increase in a load current supplied by a voltage regulator to the component.

23. The method of claim 22, wherein the plurality of instructions included in the pipeline is a first plurality of instructions, and wherein facilitating the increase in the load current supplied by the voltage regulator to the component comprises:

facilitating the component to execute a second plurality of instructions that are not included in the instruction pipeline.

24. The method of claim 23, wherein the second plurality of instructions are dummy instructions that are to generate useless results from the component.

25. The method of claim 23, further comprising:

refraining from facilitating the component to execute the second plurality of instructions, once the component starts executing the first plurality of instructions.