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1. (WO2019027278) CHIP PACKAGE AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2019/027278 International Application No.: PCT/KR2018/008816
Publication Date: 07.02.2019 International Filing Date: 03.08.2018
IPC:
H01L 23/28 (2006.01) ,H01L 23/485 (2006.01) ,H01L 23/48 (2006.01) ,H01L 25/07 (2006.01) ,H01L 23/528 (2006.01) ,H01L 23/00 (2006.01) ,H01L 21/56 (2006.01) ,H01L 23/498 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528
Layout of the interconnection structure
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
Applicants:
주식회사 네패스 NEPES CO., LTD. [KR/KR]; 충청북도 음성군 삼성면 금일로965번길 105 105, Geumil-ro 965beon-gil, Samseong-myeon Eumseong-gun Chungcheongbuk-do 27651, KR
Inventors:
권용태 KWON, Yong Tae; KR
이응주 LEE, Eung Ju; KR
여용운 YEO, Yong Woon; KR
박윤묵 PARK, Yun Mook; KR
김효영 KIM, Hyo Young; KR
이준규 LEE, Jun Kyu; KR
천석휘 CHEON, Seok Hwi; KR
Agent:
특허법인 이상 E-SANG PATENT & TRADEMARK LAW FIRM; 서울시 서초구 바우뫼로 188, 3층 3F., 188, Baumoe-ro Seocho-gu Seoul 06747, KR
Priority Data:
10-2017-009891104.08.2017KR
10-2017-012626328.09.2017KR
10-2017-012633428.09.2017KR
10-2017-012639828.09.2017KR
10-2018-008171713.07.2018KR
Title (EN) CHIP PACKAGE AND MANUFACTURING METHOD THEREFOR
(FR) BOÎTIER DE PUCE ET SON PROCÉDÉ DE FABRICATION
(KO) 칩 패키지 및 그 제조방법
Abstract:
(EN) Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer, without using a separate insulating layer formed on the molding layer as in the conventional art.
(FR) L'invention concerne un boîtier de puce susceptible d'améliorer la résistance d'un boîtier et de simplifier un processus de fabrication et son procédé de fabrication. La présente invention peut améliorer la durabilité du boîtier en formant en outre une couche de renforcement sur une puce en utilisant une couche adhésive et en moulant la puce et la couche de renforcement de façon à être intégrées à l'aide d'une couche de moulage. En outre, la résistance du boîtier peut être améliorée en ayant une structure dans laquelle des billes de soudure sont formées entre un substrat de base et une couche de recâblage et intégrées à la couche de moulage et une couche de câblage peut être formée directement sur la couche de moulage en utilisant du polyimide (PI) en tant que couche de moulage, sans utiliser une couche isolante séparée formée sur la couche de moulage comme dans l'état de la technique classique.
(KO) 패키지의 강도를 향상시키고, 제조 공정을 단순화할 수 있는 칩 패키지 및 이의 제조방법이 개시된다. 이는 칩 상에 접착층을 이용하여 보강층을 추가로 형성하고, 칩과 보강층을 몰딩층을 이용하여 일체화하도록 몰딩함으로써 패키지의 내구성을 향상시킬 수 있다. 또한, 베이스 기판과 재배선층 사이에 솔더볼을 형성하여 몰딩층으로 일체화하는 구조를 취함으로써 패키지의 강도를 향상시킬 수 있으며, 몰딩층으로 폴리이미드(PI)를 사용함으로써 종래와 같이 몰딩층 상에 형성된 별도의 절연층을 소모하지 않고 몰딩층 상에 바로 배선층을 형성할 수 있다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)