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1. (WO2019027192) SEMICONDUCTOR DEVICE PACKAGE AND LIGHT SOURCE DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/027192 International Application No.: PCT/KR2018/008583
Publication Date: 07.02.2019 International Filing Date: 27.07.2018
IPC:
H01L 33/48 (2010.01) ,H01L 33/40 (2010.01) ,H01L 33/20 (2010.01) ,H01L 33/10 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
36
characterised by the electrodes
40
Materials therefor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
20
with a particular shape, e.g. curved or truncated substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
10
with a light reflecting structure, e.g. semiconductor Bragg reflector
Applicants:
엘지이노텍 주식회사 LG INNOTEK CO., LTD. [KR/KR]; 서울시 중구 후암로 98 98, Huam-ro Jung-gu Seoul 04637, KR
Inventors:
김기석 KIM, Ki Seok; KR
박희정 PARK, Hee Jeong; KR
송준오 SONG, June O; KR
임창만 LIM, Chang Man; KR
Agent:
허용록 HAW, Yong Noke; KR
Priority Data:
10-2017-009914604.08.2017KR
Title (EN) SEMICONDUCTOR DEVICE PACKAGE AND LIGHT SOURCE DEVICE
(FR) BOÎTIER DE DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF DE SOURCE DE LUMIÈRE
(KO) 반도체 소자 패키지 및 광원 장치
Abstract:
(EN) A semiconductor device package provided in an embodiment comprises: a first and a second frame disposed to be spaced apart from each other; a body disposed between the first and the second frame; and a semiconductor device disposed on the first and the second frame and comprising a semiconductor layer and a first and a second electrode arranged on the semiconductor layer, wherein the first and the second frame comprise a first metal layer having multiple pores, and the first metal layer of the first and the second frame may comprise coupling parts in areas where the first metal layer overlaps the first and the second electrode, respectively.
(FR) Un boîtier de dispositif à semi-conducteur selon un mode de réalisation de la présente invention comprend : un premier et un second cadre disposés de façon à être espacés l'un de l'autre ; un corps disposé entre le premier et le second cadre ; et un dispositif à semi-conducteur qui est disposé sur le premier et le second cadre et qui comprend une couche semi-conductrice et une première et une seconde électrode disposées sur la couche semi-conductrice, le premier et le second cadre comprenant une première couche métallique ayant de multiples pores, et la première couche métallique du premier et du second cadre pouvant comprendre des parties de couplage dans des zones où la première couche métallique chevauche la première et la seconde électrode, respectivement.
(KO) 실시 예에 개시된 반도체 소자 패키지는, 서로 이격되어 배치되는 제1 및 제2 프레임; 상기 제1 및 제2 프레임 사이에 배치되는 몸체; 및 상기 제1 및 제2 프레임 상에 배치되며, 반도체층, 상기 반도체층 상에 배치되는 제1 및 제2 전극을 포함하는 반도체 소자; 를 포함하고, 상기 제1 및 제2 프레임은 다수의 기공을 갖는 제1 금속층을 포함하며, 상기 제1 및 제2 프레임의 제1 금속층은 상기 제1 및 제2 전극과 중첩하는 각각의 영역에 결합부를 포함할 수 있다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)