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1. (WO2019026851) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/026851 International Application No.: PCT/JP2018/028481
Publication Date: 07.02.2019 International Filing Date: 30.07.2018
IPC:
H01L 21/331 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/60 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01) ,H01L 29/737 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
328
Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors
33
the devices comprising three or more electrodes
331
Transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
737
Hetero-junction transistors
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
黒川 敦 KUROKAWA Atsushi; JP
Agent:
木村 満 KIMURA Mitsuru; JP
Priority Data:
2017-14944801.08.2017JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMICONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) This semiconductor device (100) is provided with: an HBT; emitter wiring (14) which is connected to an emitter electrode (6) of the HBT and covers the HBT; a passivation film (15) having an opening (13) on the HBT when viewed from the top; a UBM layer (17) which is connected to the emitter wiring (14) through the opening (13) and formed from a refractory metal to have a thickness of 300 nm or more; and a pillar bump (20) which is disposed on the UBM layer (17) and has a metal post (18) and a solder layer (19). The UBM layer (17) functions as a stress relaxation layer, thereby relaxing the stress on the HBT caused by the difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump (20).
(FR) La présente invention concerne un dispositif à semi-conducteur (100) qui comprend : un transistor bipolaire à hétérojonction (HBT pour Heterojunction Bipolar Transistor) ; un câblage d'émetteur (14) qui est raccordé à une électrode d'émetteur (6) du transistor HBT et recouvre le transistor HBT ; un film de passivation (15) ayant une ouverture (13) sur le transistor HBT lorsqu'il est vu depuis le dessus ; une couche de métal sous bosse (UBM pour Under Bump Metal) (17) qui est raccordée au câblage d'émetteur (14) à travers l'ouverture (13) et formée à partir d'un métal réfractaire pour avoir une épaisseur égale ou supérieure à 300 nm ; et une bosse de pilier (20) qui est disposée sur la couche de métal UBM (17) et comporte un montant métallique (18) et une couche de brasure (19). La couche de métal UBM (17) fait office de couche de relaxation de contrainte, ce qui permet de relâcher la contrainte sur le transistor HBT provoquée par la différence de coefficient de dilatation thermique entre un matériau à base de GaAs de chaque couche constituant le transistor HBT et la bosse de pilier (20).
(JA) 半導体装置(100)は、HBTと、HBTのエミッタ電極(6)に接続され、HBTを覆うエミッタ配線(14)と、平面視でHBT上に開口(13)を備えるパッシベーション膜(15)と、開口(13)を介してエミッタ配線(14)に接続され、高融点金属から厚さ300nm以上に形成されたUBM層(17)と、UBM層(17)上に配置され、メタルポスト(18)とハンダ層(19)とを備えるピラーバンプ(20)と、から構成される。UBM層(17)が応力緩和層として機能し、HBTを構成する各層のGaAs系の材料とピラーバンプ(20)との熱膨張率の差よるHBTへの応力が緩和される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)