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1. (WO2019026812) ACTIVE MATRIX SUBSTRATE, MICROFLUIDIC DEVICE PROVIDED WITH SAME, METHOD FOR PRODUCING SAID ACTIVE MATRIX SUBSTRATE, AND METHOD FOR PRODUCING SAID MICROFLUIDIC DEVICE
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Pub. No.: WO/2019/026812 International Application No.: PCT/JP2018/028334
Publication Date: 07.02.2019 International Filing Date: 27.07.2018
IPC:
H01L 27/12 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
辻埜 和也 TSUJINO, Kazuya; --
寺西 知子 TERANISHI, Tomoko; --
蜂谷 篤史 HACHIYA, Atsushi; --
古川 博章 FURUKAWA, Hiroaki; --
Agent:
特許業務法人HARAKENZO WORLD PATENT & TRADEMARK HARAKENZO WORLD PATENT & TRADEMARK; 大阪府大阪市北区天神橋2丁目北2番6号 大和南森町ビル Daiwa Minamimorimachi Building, 2-6, Tenjinbashi 2-chome Kita, Kita-ku, Osaka-shi, Osaka 5300041, JP
Priority Data:
2017-15099603.08.2017JP
Title (EN) ACTIVE MATRIX SUBSTRATE, MICROFLUIDIC DEVICE PROVIDED WITH SAME, METHOD FOR PRODUCING SAID ACTIVE MATRIX SUBSTRATE, AND METHOD FOR PRODUCING SAID MICROFLUIDIC DEVICE
(FR) SUBSTRAT MATRICIEL ACTIF, DISPOSITIF MICROFLUIDIQUE COMPRENANT CELUI-CI, PROCÉDÉ DE PRODUCTION DUDIT SUBSTRAT MATRICIEL ACTIF ET PROCÉDÉ DE PRODUCTION DUDIT DISPOSITIF MICROFLUIDIQUE
(JA) アクティブマトリクス基板、それを備えた微小流体装置およびそれらの製造方法
Abstract:
(EN) Provided are: an active matrix substrate which has a decreased drive voltage, while exhibiting excellent adhesion between a dielectric layer and a water repellent layer; and a microfluidic device which is provided with this active matrix substrate. An active matrix substrate (1) which sequentially comprises, on a first substrate (11), an array electrode (13), a dielectric layer (16) that covers the array electrode (13), and a first water repellent layer (18) in this order, and which is characterized in that: the dielectric layer (16) comprises a silicon nitride film which is positioned on a surface that is in contact with the first water repellent layer (18); and the silicon nitride film has a superficial region (17), which contains oxygen, in a surface that is in contact with the first water repellent layer (18).
(FR) L'invention concerne : un substrat matriciel actif qui a une tension d'attaque réduite, tout en présentant une excellente adhérence entre une couche diélectrique et une couche hydrofuge; et un dispositif microfluidique qui comprend ce substrat matriciel actif. Un substrat matriciel actif (1) comprend séquentiellement, sur un premier substrat (11), une électrode de réseau (13), une couche diélectrique (16) qui recouvre l'électrode de réseau (13), et une première couche hydrofuge (18) dans cet ordre, et qui est caractérisé en ce que : la couche diélectrique (16) comprend un film de nitrure de silicium qui est positionné sur une surface qui est en contact avec la première couche hydrofuge (18); et le film de nitrure de silicium a une région superficielle (17), qui contient de l'oxygène, dans une surface qui est en contact avec la première couche hydrofuge (18).
(JA) 駆動電圧が低減され、且つ、誘電体層と撥水層との密着性に優れるアクティブマトリクス基板、及びそれを備えた微小流体装置を提供する。第1基板(11)上に、アレイ電極(13)、上記アレイ電極(13)を覆う誘電体層(16)、及び第1撥水層(18)をこの順に有するアクティブマトリクス基板(1)であって、上記誘電体層(16)は、上記第1撥水層(18)と接する側に位置する窒化シリコン膜を含み、上記窒化シリコン膜は、上記第1撥水層(18)と接する側の表面に、酸素を含有する表層領域(17)を有することを特徴とする、アクティブマトリクス基板(1)。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)