Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019026803) SUBSTRATE FOR PATTERN FORMATION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/026803 International Application No.: PCT/JP2018/028306
Publication Date: 07.02.2019 International Filing Date: 27.07.2018
IPC:
B32B 27/00 (2006.01) ,B05D 1/32 (2006.01) ,B05D 7/24 (2006.01) ,H05K 1/02 (2006.01) ,H05K 3/12 (2006.01)
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
B PERFORMING OPERATIONS; TRANSPORTING
05
SPRAYING OR ATOMISING IN GENERAL; APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
D
PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
1
Processes for applying liquids or other fluent materials
32
using means for protecting parts of a surface not to be coated, e.g. using stencils, resists
B PERFORMING OPERATIONS; TRANSPORTING
05
SPRAYING OR ATOMISING IN GENERAL; APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
D
PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL
7
Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
24
for applying particular liquids or other fluent materials
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
10
in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
12
using printing techniques to apply the conductive material
Applicants:
ダイキン工業株式会社 DAIKIN INDUSTRIES, LTD. [JP/JP]; 大阪府大阪市北区中崎西2丁目4番12号梅田センタービル Umeda Center Building, 4-12, Nakazaki-Nishi 2-Chome, Kita-ku, Osaka-shi, Osaka 5308323, JP
Inventors:
本多 義昭 HONDA, Yoshiaki; JP
Agent:
山尾 憲人 YAMAO, Norihito; JP
吉田 環 YOSHIDA, Tamaki; JP
Priority Data:
2017-15183804.08.2017JP
Title (EN) SUBSTRATE FOR PATTERN FORMATION
(FR) SUBSTRAT DESTINÉ À LA FORMATION DE MOTIF
(JA) パターン形成用基体
Abstract:
(EN) A substrate for pattern formation has at least a base material and a portion derived from a perfluoro(poly)ether-group-containing silane compound, the base material having at least one main surface that has a first region and a second region, which is a pattern formation region adjacent to the first region, and the portion derived from a perfluoro(poly)ether-group-containing silane compound being disposed in the first region.
(FR) L’invention concerne un substrat destiné à la formation de motif présentant au moins un matériau de base et une partie dérivée d'un composé de silane contenant un groupe (poly)éther perfluoré, le matériau de base ayant au moins une surface principale qui a une première région et une seconde région, qui est une région de formation de motif adjacente à la première région, et la partie dérivée d'un composé de silane contenant un groupe (poly)éther perfluoré étant disposée dans la première région.
(JA) 少なくとも、基材と、パーフルオロ(ポリ)エーテル基含有シラン化合物に由来する部分とを有し、基材は、第1の領域、および、該第1の領域と隣接するパターン形成用領域である第2の領域を有する少なくとも1の主面を有し、パーフルオロ(ポリ)エーテル基含有シラン化合物に由来する部分は、第1の領域に配置されている、パターン形成用基体。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)