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1. (WO2019026741) SUBSTRATE AND METHOD FOR PRODUCING SUBSTRATE
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Pub. No.: WO/2019/026741 International Application No.: PCT/JP2018/028001
Publication Date: 07.02.2019 International Filing Date: 26.07.2018
IPC:
H01L 29/786 (2006.01) ,G09F 9/00 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/3065 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
松本 龍児 MATSUMOTO, Ryuji; --
近間 義雅 CHIKAMA, Yoshimasa; --
古川 弘和 FURUKAWA, Hirokazu; --
Agent:
特許業務法人 安富国際特許事務所 YASUTOMI & ASSOCIATES; 大阪府大阪市淀川区宮原3丁目5番36号 5-36, Miyahara 3-chome, Yodogawa-ku, Osaka-shi, Osaka 5320003, JP
Priority Data:
2017-15026802.08.2017JP
Title (EN) SUBSTRATE AND METHOD FOR PRODUCING SUBSTRATE
(FR) SUBSTRAT ET PROCÉDÉ DE PRODUCTION DE SUBSTRAT
(JA) 基板及び基板の製造方法
Abstract:
(EN) The present invention provides: a substrate which enables a hole that penetrates a plurality of insulating films to be reduced in size, while exhibiting excellent coverage by and adhesion to an upper layer on the plurality of insulating films in a portion where the hole is formed; and a method for producing this substrate, by which the above-described hole is able to be formed at a time in the above-described plurality of insulating films by means of dry etching. A substrate according to the present invention is sequentially provided with an insulating substrate, a lower layer, a first insulating film, a second insulating film and an upper layer, and is provided with a hole which penetrates at least the first insulating film and the second insulating film and reaches at least one of the lower layer and the insulating substrate. Within the region where the hole is formed, the first insulating film has a projection which protrudes beyond an end of the second insulating film, said end being in contact with the first insulating film; a stepped structure is configured to comprise the projection of the first insulating film and the end of the second insulating film; the upper layer covers the stepped structure; and the upper surface of the projection of the first insulating film and the upper surface of a portion of the first insulating film, said portion being positioned below the end of the second insulating film, are on the same plane.
(FR) La présente invention concerne : un substrat qui permet de diminuer la taille d'un trou qui pénètre une pluralité de films isolants, tout en présentant une excellente couverture par une couche supérieure et une adhérence à cette dernière sur la pluralité de films isolants dans une partie où est formé le trou ; et un procédé de production de ce substrat, par lequel il est possible de former le trou décrit ci-dessus à la fois dans la pluralité susmentionnée de films isolants au moyen d'une gravure sèche. Un substrat selon la présente invention est pourvu successivement d'un substrat isolant, d'une couche inférieure, d'un premier film isolant, d'un second film isolant et d'une couche supérieure, et est pourvu d'un trou qui pénètre au moins le premier film isolant et le second film isolant et qui atteint la couche inférieure et/ou le substrat isolant. Dans la région où est formé le trou, le premier film isolant comporte une saillie qui fait saillie au-delà d'une extrémité du second film isolant, ladite extrémité étant en contact avec le premier film isolant ; une structure étagée est conçue pour comprendre la saillie du premier film isolant et l'extrémité du second film isolant ; la couche supérieure recouvre la structure étagée ; et la surface supérieure de la saillie du premier film isolant et la surface supérieure d'une partie du premier film isolant sont sur le même plan, ladite partie étant positionnée au-dessous de l'extrémité du second film isolant.
(JA) 本発明は、複数の絶縁膜を貫通する孔の大きさを縮小でき、かつ、その孔の形成部における複数の絶縁膜上の上層のカバレッジと密着性とに優れた基板、及び、上記複数の絶縁膜に上記孔をドライエッチングにより一括形成可能な上記基板の製造方法を提供する。 本発明の基板は、絶縁基板と、下層と、第1絶縁膜と、第2絶縁膜と、上層と、を順に備え、少なくとも上記第1絶縁膜及び上記第2絶縁膜を貫通して上記下層及び上記絶縁基板の少なくとも一方に達する孔が設けられ、上記孔が設けられた領域内に、上記第1絶縁膜は、上記第2絶縁膜の、上記第1絶縁膜に接する端部から突出した突出部を有し、上記第1絶縁膜の上記突出部と、上記第2絶縁膜の上記端部とを含んで構成される階段構造が設けられ、上記上層は、上記階段構造を覆い、上記第1絶縁膜の上記突出部の上面と、上記第1絶縁膜の、上記第2絶縁膜の上記端部の下に位置する部分の上面とは、同一平面上にある。
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African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)