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1. (WO2019026719) SOLID-STATE IMAGING DEVICE
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Pub. No.: WO/2019/026719 International Application No.: PCT/JP2018/027845
Publication Date: 07.02.2019 International Filing Date: 25.07.2018
IPC:
H01L 27/146 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
Applicants:
SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
KOBAYASHI Kenji; JP
WAKANO Toshifumi; JP
OTAKE Yusuke; JP
Agent:
NISHIKAWA Takashi; JP
INAMOTO Yoshio; JP
Priority Data:
2017-15198004.08.2017JP
Title (EN) SOLID-STATE IMAGING DEVICE
(FR) DISPOSITIF D'IMAGERIE À SEMI-CONDUCTEUR
Abstract:
(EN) An imaging device includes a first chip (12). The first chip includes a first pixel (21) and a second pixel (21). The first pixel includes a first anode region (31) and a first cathode region (32), and the second pixel includes a second anode region (31) and a second cathode region (32). The first chip includes a first wiring layer (23). The first wiring layer includes a first anode electrode (37), a first anode via (38) coupled to the first anode electrode (37) and the first anode region (31), and a second anode via (38) coupled to the first anode electrode (37) and the second anode region (31).
(FR) L'invention concerne un dispositif d'imagerie qui comprend une première puce (12). La première puce comprend un premier pixel (21) et un second pixel (21). Le premier pixel comprend une première région d'anode (31) et une première région de cathode (32), et le second pixel comprend une seconde région d'anode (31) et une seconde région de cathode (32). La première puce comprend une première couche de câblage (23). La première couche de câblage comprend une première électrode d'anode (37), un premier trou d'interconnexion d'anode (38) couplé à la première électrode d'anode (37) et à la première région d'anode (31), et un second trou d'interconnexion d'anode (38) couplé à la première électrode d'anode (37) et à la seconde région d'anode (31).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)