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1. (WO2019026695) MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING MULTILAYER SUBSTRATE
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Pub. No.: WO/2019/026695 International Application No.: PCT/JP2018/027722
Publication Date: 07.02.2019 International Filing Date: 24.07.2018
IPC:
H05K 3/46 (2006.01) ,H05K 1/16 (2006.01) ,H05K 3/20 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
10
in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
20
by affixing prefabricated conductor pattern
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
郷地 直樹 GOUCHI, Naoki; JP
伊藤 慎悟 ITO, Shingo; JP
Agent:
山尾 憲人 YAMAO, Norihito; JP
柳橋 泰雄 YANAGIHASHI, Yasuo; JP
Priority Data:
2017-14995402.08.2017JP
Title (EN) MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING MULTILAYER SUBSTRATE
(FR) SUBSTRAT MULTICOUCHE ET SON PROCÉDÉ DE FABRICATION
(JA) 多層基板および多層基板の製造方法
Abstract:
(EN) Provided is a multilayer substrate with which it is possible to inhibit conductor pattern misalignment using a simple method, even when the number of laminated layers is high. A multilayer substrate 1 formed by laminating a plurality of insulating substrates 2 including an insulating substrate 2 on which a plurality of conductor patterns 3 is formed, wherein: one main surface 3a of the conductor patterns 3 has a greater surface roughness than that of the other main surface 3b; the conductor patterns 3 are embedded in the insulating substrate 2 so that the one main surface 3a is located inside the insulating substrate 2 and the other main surface 3b projects from the surface of the insulating substrate 2; the conductor patterns 3 located in the insulating substrate 2 have a portion at which the width L1 located on the obverse surface side and the width L2 located on the interior side have the relationship L1 < L2.
(FR) L'invention concerne un substrat multicouche permettant d'empêcher un mésalignement de motifs conducteurs au moyen d'un procédé simple, même quand le nombre de couches stratifiées est élevé. Un substrat multicouche (1) est formé par stratification d'une pluralité de substrats isolants (2) comprenant un substrat isolant (2) sur lequel une pluralité de motifs conducteurs (3) sont formés, une surface principale (3a) des motifs conducteurs (3) présentant une rugosité de surface supérieure à celle de l'autre surface principale (3b), les motifs conducteurs (3) étant intégrés dans le substrat isolant (2) de telle sorte que la surface principale (3a) se trouve dans le substrat isolant (2) et l'autre surface principale (3b) fait saillie à partir de la surface du substrat isolant (2), et les motifs conducteurs (3) situés dans le substrat isolant (2) comprenant une partie au niveau de laquelle la largeur L1 située sur le côté de surface apparente et la largeur L2 située sur le côté intérieur ont la relation L1 < L2.
(JA) 積層数が多い場合でも、簡単な方法で導体パターンずれを抑制することのできる多層基板を提供する。複数の導体パターン3が形成された絶縁基材2を含む複数の絶縁基材2を積層して形成される多層基板1であって、導体パターン3の一方主面3aが他方主面3bよりも表面粗さが大きく、導体パターン3は、一方主面3aが絶縁基材2の内部に位置し、他方主面3bが絶縁基材2の表面から突出するように、絶縁基材2に埋設されており、絶縁基材2の内部に位置する導体パターン3は、表面側に位置する幅L1と、内部側に位置する幅L2とが、L1<L2の関係になる部分を有する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)