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1. (WO2019026394) TRANSISTOR PRODUCTION METHOD AND TRANSISTOR
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Pub. No.: WO/2019/026394 International Application No.: PCT/JP2018/019626
Publication Date: 07.02.2019 International Filing Date: 22.05.2018
IPC:
H01L 21/336 (2006.01) ,H01L 21/203 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
203
using physical deposition, e.g. vacuum deposition, sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
株式会社ニコン NIKON CORPORATION [JP/JP]; 東京都港区港南二丁目15番3号 15-3, Konan 2-chome, Minato-ku, Tokyo 1086290, JP
Inventors:
中積 誠 NAKAZUMI Makoto; JP
西 康孝 NISHI Yasutaka; JP
Agent:
特許業務法人 湘洋内外特許事務所 SHOYO INTELLECTUAL PROPERTY FIRM; 神奈川県横浜市西区北幸二丁目15番1号 東武横浜第2ビル6階 6F, Tobu Yokohama 2ND Bldg., 15-1, Kitasaiwai 2-chome, Nishi-ku, Yokohama-shi, Kanagawa 2200004, JP
Priority Data:
2017-14874901.08.2017JP
Title (EN) TRANSISTOR PRODUCTION METHOD AND TRANSISTOR
(FR) PROCÉDÉ DE PRODUCTION DE TRANSISTOR ET TRANSISTOR
(JA) トランジスタの製造方法、及びトランジスタ
Abstract:
(EN) The invention is a production method for a transistor 1 that comprises a substrate 10, a gate electrode 12, a source electrode 14, a drain electrode 16, and a semiconductor layer 18, and includes a semiconductor layer forming step of irradiating and sputtering helicon plasma onto a raw material that is to constitute the semiconductor layer 18, thereby causing the semiconductor layer 18 to be formed.
(FR) L'invention concerne un procédé de production d'un transistor 1 qui comprend un substrat 10, une électrode de grille 12, une électrode de source 14, une électrode de drain 16, et une couche semi-conductrice 18, et comprend une étape de formation de couche semi-conductrice consistant à irradier et à pulvériser un plasma d'hélicon sur une matière première qui est destinée à constituer la couche semi-conductrice 18, ce qui provoque la formation de la couche semi-conductrice 18.
(JA) 基板10と、ゲート電極12と、ソース電極14と、ドレイン電極16と、半導体層18とを含むトランジスタ1の製造方法であって、半導体層18を構成する原料に対して、ヘリコンプラズマを照射してスパッタすることによって、半導体層18を形成させる半導体層形成工程を含む、トランジスタの製造方法。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)