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1. (WO2019026315) DISTORTION MITIGATION QUANTIZER CIRCUIT, METHOD FOR MITIGATING DISTORTION NOISE AND DIGITAL TRANSMITTER
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Pub. No.: WO/2019/026315 International Application No.: PCT/JP2018/003712
Publication Date: 07.02.2019 International Filing Date: 30.01.2018
IPC:
H03F 3/217 (2006.01) ,H03F 1/26 (2006.01) ,H03F 3/19 (2006.01) ,H03K 7/08 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
20
Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
21
with semiconductor devices only
217
Class D power amplifiers; Switching amplifiers
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
26
Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
189
High-frequency amplifiers, e.g. radio frequency amplifiers
19
with semiconductor devices only
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
7
Modulating pulses with a continuously-variable modulating signal
08
Duration or width modulation
Applicants:
MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
MA, Rui; US
TANOVIC, Omer; US
Agent:
SOGA, Michiharu; S. SOGA & CO., 8th Floor, Kokusai Building, 1-1, Marunouchi 3-chome, Chiyoda-ku, Tokyo 1000005, JP
KAJINAMI, Jun; S. SOGA & CO. 8th Floor, Kokusai Building 1-1, Marunouchi 3-chome Chiyoda-ku, Tokyo 1000005, JP
UEDA, Shunichi; S. SOGA & CO. 8th Floor, Kokusai Building 1-1, Marunouchi 3-chome Chiyoda-ku, Tokyo 1000005, JP
Priority Data:
15/669,43404.08.2017US
Title (EN) DISTORTION MITIGATION QUANTIZER CIRCUIT, METHOD FOR MITIGATING DISTORTION NOISE AND DIGITAL TRANSMITTER
(FR) CIRCUIT QUANTIFICATEUR D'ATTÉNUATION DE DISTORSION, PROCÉDÉ D'ATTÉNUATION DU BRUIT DE DISTORSION ET ÉMETTEUR NUMÉRIQUE
Abstract:
(EN) A distortion mitigation quantizer circuit includes a pre-quantizer to generate a first quantized signal having L output signal levels from an input signal and a digital pulse-width-modulation (PWM) circuit to modulate the first quantized signal using M modulating carriers with PWM carrier frequency fp and according to an over sampling ratio (OSR) N in order to generate a second quantized signal. In this case, a number of the modulating carriers M is substantially equal to twice L/N.
(FR) L'invention concerne un circuit quantificateur d'atténuation de distorsion comprenant un préquantificateur destiné à générer un premier signal quantifié ayant L niveaux de signal de sortie à partir d'un signal d'entrée et un circuit numérique de modulation en largeur d'impulsion (PWM) destiné à moduler le premier signal quantifié au moyen de M porteuses de modulation ayant une fréquence de porteuse de PWM fp et conformément à un rapport de suréchantillonnage (OSR) N afin de générer un second signal quantifié. Dans ce cas, un nombre de porteuses de modulation M est sensiblement égal à deux fois L/N.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)