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1. (WO2019025911) SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/025911 International Application No.: PCT/IB2018/055578
Publication Date: 07.02.2019 International Filing Date: 26.07.2018
IPC:
H01L 21/336 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/283 (2006.01) ,H01L 21/8242 (2006.01) ,H01L 27/108 (2006.01) ,H01L 27/1156 (2017.01) ,H01L 29/417 (2006.01) ,H01L 29/786 (2006.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8242
Dynamic random access memory structures (DRAM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
[IPC code unknown for H01L 27/1156]
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
417
carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
山崎舜平 YAMAZAKI, Shunpei; JP
松林大介 MATSUBAYASHI, Daisuke; JP
浅見良信 ASAMI, Yoshinobu; JP
Priority Data:
2017-15144604.08.2017JP
2018-02772120.02.2018JP
Title (EN) SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置、および半導体装置の作製方法
Abstract:
(EN) Provided is a semiconductor device which can be made fine or highly integrated. The semiconductor device comprises: an oxide; a first conductor and a second conductor disposed at a distance from each other and on the oxide; a first insulator that is disposed on the first conductor and the second conductor, and that has an opening formed superimposed between the first conductor and the second conductor; a third conductor disposed in the opening; and a second insulator disposed between the third conductor and the oxide, the first conductor, the second conductor and the first insulator. The second insulator has a first film thickness between the oxide and the third conductor, and has a second film thickness between the third conductor and the first conductor or second conductor, the first film thickness being thinner than the second film thickness.
(FR) La présente invention concerne un dispositif à semi-conducteur qui peut être rendu fin ou hautement intégré. Le dispositif à semi-conducteur comprend : un oxyde ; un premier conducteur et un second conducteur disposés à une certaine distance les uns des autres et sur l'oxyde ; un premier isolant qui est disposé sur le premier conducteur et le second conducteur, et qui a une ouverture formée en superposition entre le premier conducteur et le second conducteur ; un troisième conducteur disposé dans l'ouverture ; et un second isolant disposé entre le troisième conducteur et l'oxyde, le premier conducteur, le second conducteur et le premier isolant. Le second isolant a une première épaisseur de film entre l'oxyde et le troisième conducteur, et a une seconde épaisseur de film entre le troisième conducteur et le premier conducteur ou le second conducteur, la première épaisseur de film étant plus mince que la seconde épaisseur de film.
(JA) 要約書 微細化または高集積化が可能な半導体装置を提供する。 酸化物と、 酸化物上に、 互いに離して配置された第1の導電体、 および第2の導電体と、 第1の導電 体および第2の導電体上に配置され、第1の導電体と第2の導電体の間に重畳して開口が形成された 第1の絶縁体と、開口の中に配置された第3の導電体と、酸化物、第1の導電体、第2の導電体、お よび第1の絶縁体と、第3の導電体と、の間に配置された第2の絶縁体と、を有し、第2の絶縁体は、 酸化物と第3の導電体の間において、 第1の膜厚を有し、 第1の導電体または第2の導電体と第3の 導電体の間において、第2の膜厚を有し、第1の膜厚は、第2の膜厚より薄い。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)