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1. (WO2019025454) METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT
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Pub. No.: WO/2019/025454 International Application No.: PCT/EP2018/070762
Publication Date: 07.02.2019 International Filing Date: 31.07.2018
IPC:
H01L 33/54 (2010.01) ,H01L 33/56 (2010.01) ,H01L 33/60 (2010.01) ,H01L 33/50 (2010.01) ,H01L 33/58 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
52
Encapsulations
54
having a particular shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
52
Encapsulations
56
Materials, e.g. epoxy or silicone resin
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
58
Optical field-shaping elements
60
Reflective elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
50
Wavelength conversion elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
58
Optical field-shaping elements
Applicants:
OSRAM OPTO SEMICONDUCTORS GMBH [DE/DE]; Leibnizstr. 4 93055 Regensburg, DE
Inventors:
LEISEN, Daniel; DE
BRUNNER, Herbert; DE
DINU, Emilia; DE
EBERHARD, Jens; DE
KEITH, Christina; DE
PINDL, Markus; null
REESWINKEL, Thomas; DE
RICHTER, Daniel; DE
Agent:
PATENTANWALTSKANZLEI WILHELM & BECK; Prinzenstr. 13 80639 München, DE
Priority Data:
10 2017 117 441.901.08.2017DE
Title (EN) METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT
(FR) PROCÉDÉ DE FABRICATION D'UN COMPOSANT OPTOÉLECTRONIQUE
(DE) VERFAHREN ZUM HERSTELLEN EINES OPTOELEKTRONISCHEN BAUELEMENTS
Abstract:
(EN) The invention relates to a method for producing an optoelectronic component, comprising the following method steps: A support having a top side is provided. An optoelectronic semiconductor chip is arranged above the top side of the support. Furthermore, a potting material is arranged above the top side of the support, the optoelectronic semiconductor chip being embedded into the potting material. The potting material forms a potting surface. The potting material is deformed on the potting surface, wherein a topography is generated at the potting surface. The deformation of the potting material at the potting surface is carried out by a curing of the potting surface. The curing of the potting surface is accompanied by a convolution of the potting surface.
(FR) L'invention concerne un procédé de fabrication d'un composant optoélectronique comprenant les étapes suivantes. Un support présentant une face supérieure est fourni. Une puce à semi-conducteur optoélectronique est disposée au-dessus de la face supérieure du support. Une matière d’enrobage est également disposée au-dessus de la face supérieure dudit support, la puce à semi-conducteur optoélectronique étant noyée dans ladite matière d’enrobage. Cette matière d'enrobage forme une surface d’enrobage. La matière d'enrobage est mise en forme au niveau de la surface d’enrobage, une topographie étant ainsi créée au niveau de la surface d’enrobage. La mise en forme de la matière d’enrobage au niveau de la surface d'enrobage est réalisée par un durcissement de la surface d’enrobage. Le durcissement de la surface d’enrobage s'accompagne d'un pliage de la surface d’enrobage.
(DE) Ein Verfahren zum Herstellen eines optoelektronischen Bauelements weist die folgenden Verfahrensschritte auf. Ein Träger mit einer Oberseite wird bereitgestellt. Ein optoelektronischer Halbleiterchip wird über der Oberseite des Trägers angeordnet. Weiterhin wird ein Vergussmaterial über der Oberseite des Trägers angeordnet, wobei der optoelektronische Halbleiterchip in das Vergussmaterial eingebettet wird. Das Vergussmaterial bildet eine Vergussoberfläche. Das Vergussmaterial wird an der Vergussoberfläche umgeformt, wobei an der Vergussoberfläche eine Topographie erzeugt wird. Das Umformen des Vergussmaterials an der Vergussoberfläche erfolgt durch eine Härtung der Vergussoberfläche. Mit der Härtung der Vergussoberfläche geht eine Faltung der Vergussoberfläche einher.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: German (DE)
Filing Language: German (DE)