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1. (WO2019025447) PHASE-LOCKED LOOP CIRCUIT
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Pub. No.:
WO/2019/025447
International Application No.:
PCT/EP2018/070748
Publication Date:
07.02.2019
International Filing Date:
31.07.2018
IPC:
H03L 1/00
(2006.01) ,
H03L 7/08
(2006.01)
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
1
Stabilisation of generator output against variations of physical values, e.g. power supply
H
ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
08
Details of the phase-locked loop
Applicants:
AMS AG
[AT/AT]; Schloss Premstätten Tobelbader Str. 30 8141 Premstätten, AT
Inventors:
CHEN, Jia Sheng
; AT
SCHATZBERGER, Gregor
; AT
Agent:
EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH
; Schloßschmidstr. 5 80639 München, DE
Priority Data:
17184454.1
02.08.2017
EP
Title
(EN)
PHASE-LOCKED LOOP CIRCUIT
(FR)
CIRCUIT À BOUCLE DE VERROUILLAGE DE PHASE
Abstract:
(EN)
A phase-locked loop circuit comprises an oscillator (308) having a plurality of operating curves and being suitable for generating an output signal (FOSC). In a calibration state the oscillator(308) is trimmed to an operating curve for use in a normal operation state. The phase-locked loop circuit further comprises a phase/frequency detector (302) being suitable for generating at least one error signal (FE) based on an input signal (FIN) and a feedback signal (FDIV) generated on the basis of the output signal (FOSC). The phase-locked loop circuit further comprises a loop filter (303) being suitable for generating a loop-filter signal (VLF) based on the at least one error signal (FE, UP, DOWN), the loop-filter signal (VLF) being applied to the oscillator (308) in the normal operation state. The phase-locked loop circuit further comprises a calibration circuit (312) being suitable for trimming the oscillator (308) to the operating curve for use in the normal operation state on the basis of the at least one error signal.
(FR)
Un circuit à boucle de verrouillage de phase comprend un oscillateur (308) ayant une pluralité de courbes de fonctionnement et étant conçu pour générer un signal de sortie (FOSC). Dans un état d'étalonnage, l'oscillateur (308) est ajusté sur une courbe de fonctionnement pour une utilisation dans un état de fonctionnement normal. Le circuit à boucle de verrouillage de phase comprend en outre un détecteur de phase/fréquence (302) conçu pour générer au moins un signal d'erreur (FE) sur la base d'un signal d'entrée (FIN) et d'un signal de rétroaction (FDIV) généré sur la base du signal de sortie (FOSC). Le circuit à boucle de verrouillage de phase comprend en outre un filtre à boucle (303) conçu pour générer un signal de filtre à boucle (VLF) sur la base du ou des signaux d'erreur (FE, UP, DOWN), le signal de filtre à boucle (VLF) étant appliqué à l'oscillateur (308) dans l'état de fonctionnement normal. Le circuit de boucle de verrouillage de phase comprend en outre un circuit d'étalonnage (312) conçu pour ajuster l'oscillateur (308) à la courbe de fonctionnement pour une utilisation dans l'état de fonctionnement normal sur la base du ou des signaux d'erreur.
Designated States:
AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language:
English (
EN
)
Filing Language:
English (
EN
)