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1. (WO2019024906) LDMOS COMPONENT, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
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Pub. No.: WO/2019/024906 International Application No.: PCT/CN2018/098447
Publication Date: 07.02.2019 International Filing Date: 03.08.2018
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
无锡华润上华科技有限公司 CSMC TECHNOLOGIES FAB2 CO., LTD. [CN/CN]; 中国江苏省无锡市 新区新洲路8号 No. 8 Xinzhou Road, New District Wuxi, Jiangsu 214028, CN
Inventors:
金华俊 JIN, Huajun; CN
孙贵鹏 SUN, Guipeng; CN
金宏峰 JIN, Hongfeng; CN
Agent:
广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE; 中国广东省广州市天河区珠江东路6号4501房 (部位:自编01-03和08-12单元)(仅限办公用途) Room 4501, No. 6 Zhujiang East Road, Tianhe District, Guangzhou Guangdong 510623, CN
Priority Data:
201710660988.804.08.2017CN
Title (EN) LDMOS COMPONENT, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
(FR) COMPOSANT LDMOS, SON PROCÉDÉ DE FABRICATION ET DISPOSITIF ÉLECTRONIQUE
(ZH) 一种LDMOS器件及其制造方法和电子装置
Abstract:
(EN) Provided in the present invention are an LDMOS component, a manufacturing method therefor, and an electronic device, comprising: a semiconductor substrate (100); a drift area (101) provided in the semiconductor substrate; a gate electrode structure (103) provided on a part of the surface of the semiconductor substrate and covers a part of the surface of the drift area; a source electrode (1052) and a drain electrode (1051) respectively provided in the semiconductor substrate on either side of the gate electrode structure, where the drain electrode is provided in the drift area and is separated from the gate electrode structure; a metal silicide barrier layer (106) covering the surface of at least a part of the semiconductor substrate between the gate electrode structure and the drain electrode; and a first contact hole (1081) provided on the surface of at least a part of the metal silicide barrier layer.
(FR) La présente invention concerne un composant LDMOS, son procédé de fabrication, et un dispositif électronique, comprenant : un substrat semi-conducteur (100) ; une zone de dérive (101) disposée dans le substrat semi-conducteur ; une structure d'électrode de grille (103) disposée sur une partie de la surface du substrat semi-conducteur et recouvrant une partie de la surface de la zone de dérive ; une électrode de source (1052) et une électrode de drain (1051) disposées respectivement dans le substrat semi-conducteur de chaque côté de la structure d'électrode de grille, l'électrode de drain étant disposée dans la zone de dérive et étant séparée de la structure d'électrode de grille; une couche barrière en siliciure métallique (106) recouvrant la surface d'au moins une partie du substrat semi-conducteur entre la structure d'électrode de grille et l'électrode de drain; et un premier trou de contact (1081) disposé sur la surface d'au moins une partie de la couche barrière en siliciure métallique.
(ZH) 本发明提供一种LDMOS器件及其制造方法和电子装置,包括:半导体衬底(100);漂移区(101),设置在半导体衬底中;栅极结构(103),设置在半导体衬底的部分表面上,并覆盖部分漂移区的表面;源极(1052)和漏极(1051),分别设置在栅极结构两侧的半导体衬底中,其中,漏极设置在漂移区内并与栅极结构之间存在间隔;金属硅化物阻挡层(106),覆盖栅极结构和漏极之间的至少部分半导体衬底的表面;第一接触孔(1081),设置在至少部分金属硅化物阻挡层的表面上。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)