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1. (WO2019024565) WIRING STRUCTURE AND PREPARATION METHOD THEREFOR, OLED ARRAY SUBSTRATE AND DISPLAY DEVICE
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Pub. No.: WO/2019/024565 International Application No.: PCT/CN2018/086460
Publication Date: 07.02.2019 International Filing Date: 11.05.2018
IPC:
H01L 27/12 (2006.01) ,H01L 27/32 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
32
with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
肖丽 XIAO, Li; CN
玄明花 XUAN, Minghua; CN
杨盛际 YANG, Shengji; CN
陈小川 CHEN, Xiaochuan; CN
王磊 WANG, Lei; CN
付杰 FU, Jie; CN
卢鹏程 LU, Pengcheng; CN
刘冬妮 LIU, Dongni; CN
Agent:
北京市柳沈律师事务所 LIU, SHEN & ASSOCIATES; 中国北京市 海淀区彩和坊路10号1号楼10层 10th Floor, Building 1, 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201710650543.102.08.2017CN
Title (EN) WIRING STRUCTURE AND PREPARATION METHOD THEREFOR, OLED ARRAY SUBSTRATE AND DISPLAY DEVICE
(FR) STRUCTURE DE CÂBLAGE ET SON PROCÉDÉ DE PRÉPARATION, ET SUBSTRAT DE RÉSEAU OLED ET DISPOSITIF D'AFFICHAGE
(ZH) 布线结构及其制备方法、OLED阵列基板以及显示装置
Abstract:
(EN) A wiring structure and a preparation method therefor, an organic light-emitting diode (OLED) array substrate and a display device. The wiring structure (100) comprises: a base substrate (101, 201), wherein the base substrate (101, 201) comprises a first surface (102) and a second surface (103), which are opposite each other; and a first conductive pattern (104) arranged on the first surface (102) of the base substrate (101, 201) and a second conductive pattern (105) arranged on the second surface (103) of the base substrate (101, 201), wherein the first conductive pattern (104) is connected to the second conductive pattern (105) by means of a through-hole pattern (106) penetrating the base substrate (101, 201). The connection of the first conductive pattern (104) to the second conductive pattern (105) by means of the through-hole pattern (106) penetrating the base substrate (101, 201) may reduce the resistance of the first conductive pattern (104), and when the wiring structure (100) is applied in the organic light-emitting diode (OLED) array substrate, the uniformity of display can be improved.
(FR) L'invention concerne une structure de câblage et son procédé de préparation, et un substrat de réseau de diodes électroluminescentes organiques (OLED) et un dispositif d'affichage. La structure de câblage (100) comprend : un substrat de base (101, 201), le substrat de base (101, 201) comprenant une première surface (102) et une seconde surface (103), qui sont opposées l'une à l'autre; et un premier motif conducteur (104) disposé sur la première surface (102) du substrat de base (101, 201) et un second motif conducteur (105) disposé sur la seconde surface (103) du substrat de base (101, 201), le premier motif conducteur (104) étant connecté au second motif conducteur (105) au moyen d'un motif de trou traversant (106) pénétrant dans le substrat de base (101, 201). La connexion du premier motif conducteur (104) au second motif conducteur (105) au moyen du motif de trou traversant (106) pénétrant dans le substrat de base (101, 201) peut réduire la résistance du premier motif conducteur (104), et lorsque la structure de câblage (100) est appliquée dans le substrat de réseau de diodes électroluminescentes organiques (OLED), l'uniformité d'affichage peut être améliorée.
(ZH) 一种布线结构及其制备方法、有机发光二极管(OLED)阵列基板以及显示装置,该布线结构(100)包括:衬底基板(101,201),该衬底基板(101,201)包括彼此相对的第一表面(102)和第二表面(103);设置在所述衬底基板(101,201)的所述第一表面(102)上的第一导电图案(104)和设置在所述衬底基板(101,201)的所述第二表面(103)上的第二导电图案(105);其中,所述第一导电图案(104)和所述第二导电图案(105)通过贯穿所述衬底基板(101,201)的通孔图案(106)连接。第一导电图案(104)和第二导电图案(105)通过贯穿衬底基板(101,201)的通孔图案(106)连接可以减小第一导电图案(104)的电阻,将该布线结构(100)应用于有机发光二极管(OLED)阵列基板中时,可以改善显示的均一性。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)