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1. (WO2019023962) PIXEL CIRUIT, ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF COMPENSATING THRESHOLD VOLTAGE OF DRIVING TRANSISTOR
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Pub. No.: WO/2019/023962 International Application No.: PCT/CN2017/095577
Publication Date: 07.02.2019 International Filing Date: 02.08.2017
IPC:
G09G 3/32 (2016.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
22
using controlled light sources
30
using electroluminescent panels
32
semiconductive, e.g. diodes
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
GAI, Cuili; CN
WU, Zhongyuan; CN
ZHANG, Baoxia; CN
WANG, Ling; CN
LIN, Yicheng; CN
LI, Quanhu; CN
LIU, Fang; CN
Agent:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
Title (EN) PIXEL CIRUIT, ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL, DISPLAY APPARATUS, AND METHOD OF COMPENSATING THRESHOLD VOLTAGE OF DRIVING TRANSISTOR
(FR) CIRCUIT DE PIXEL, PANNEAU D'AFFICHAGE À DIODE ÉLECTROLUMINESCENTE ORGANIQUE À MATRICE ACTIVE, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE COMPENSATION DE TENSION DE SEUIL DE TRANSISTOR D'ATTAQUE
Abstract:
(EN) A pixel circuit in an active matrix organic light-emitting diode (AMOLED) display panel. The pixel circuit includes a first transistor (T1) having a bottom gate (BG) and a top gate (TG), a drain supplied with a high-level power-supply voltage (VDD), and a source coupled to a light-emitting diode (LED). The bottom gate (BG) is provided with a first voltage signal (Vdata) and the source is provided with a second voltage signal (Vsense) in a compensation period during which a present value of a threshold voltage of the first transistor (T1) is sensed at the source and a third voltage signal (Vtg) is determined based on the present value of the threshold voltage. The top gate (TG) is configured to be provided with the third voltage signal (Vtg) in an emission period to reduce the present value of the threshold voltage.
(FR) La présente invention concerne un circuit de pixel dans un panneau d'affichage à diode électroluminescente organique à matrice active (AMOLED). Le circuit de pixel comprend un premier transistor (T1) ayant une grille inférieure (BG) et une grille supérieure (TG), un drain alimenté avec une tension d'alimentation électrique de haut niveau (VDD), et une source couplée à une diode électroluminescente (DEL). La grille inférieure (BG) est pourvue d'un premier signal de tension (Vdata) et la source est pourvue d'un second signal de tension (Vsense) dans une période de compensation pendant laquelle une valeur actuelle d'une tension de seuil du premier transistor (T1) est détectée au niveau de la source et un troisième signal de tension (Vtg) est déterminé sur la base de la valeur actuelle de la tension de seuil. La grille supérieure (TG) est configurée pour être pourvue du troisième signal de tension (Vtg) dans une période d'émission pour réduire la valeur actuelle de la tension de seuil.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)