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1. (WO2019023910) DATA PROCESSING METHOD AND DEVICE
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Pub. No.: WO/2019/023910 International Application No.: PCT/CN2017/095334
Publication Date: 07.02.2019 International Filing Date: 31.07.2017
IPC:
G06F 7/57 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
57
Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483-G06F7/556174
Applicants:
深圳市大疆创新科技有限公司 SZ DJI TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省 深圳市南山区高新区南区粤兴一道9号香港科大深圳产学研大楼6楼 6F, HKUST SZ IER BLdg, No. 9 Yuexing 1st Rd, Hi-Tech Park (South), Nanshan District, Shenzhen Guangdong 518057, CN
Inventors:
仇晓颖 QIU, Xiaoying; CN
韩彬 HAN, Bin; CN
Agent:
中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; 中国北京市 海淀区西三环北路87号4-1105室 Suite 4-1105, No. 87, West 3rd Ring North Rd., Haidian District Beijing 100089, CN
Priority Data:
Title (EN) DATA PROCESSING METHOD AND DEVICE
(FR) PROCÉDÉ ET DISPOSITIF DE TRAITEMENT DE DONNÉES
(ZH) 数据处理方法和设备
Abstract:
(EN) A data processing circuit comprises: a computing unit, comprising adders and multiple N-bit multipliers; an input unit, configured to provide inputs to the multipliers; and an output unit, configured to output a computing result of the computing unit, the adders comprising an N-bit adder and an 2N-bit adder, N=2n, and n being a natural number greater than 0. Also provided are a method for operating the data processing circuit and a corresponding device.
(FR) Selon l'invention, un circuit de traitement de données comprend : une unité de calcul, comprenant des additionneurs et de multiples multiplicateurs à N bits ; une unité d'entrée, configurée pour fournir des entrées aux multiplicateurs ; et une unité de sortie, configurée pour fournir en sortie un résultat de calcul de l'unité de calcul, les additionneurs comprenant un additionneur à N bits et un additionneur à 2N bits, N = 2n, et n étant un nombre naturel supérieur à 0. L'invention concerne également un procédé d'utilisation du circuit de traitement de données et un dispositif correspondant.
(ZH) 一种数据处理电路,包括:计算单元,包括加法器和多个N位乘法器;输入单元,被配置为向所述乘法器提供输入;以及输出单元,被配置为输出所述计算单元的计算结果;其中,所述加法器包括N位加法器和2N位加法器,N=2n,n为大于0的自然数。还提供了一种操作数据处理电路的方法以及相应的设备。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)