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1. (WO2019021903) LAMINATED ELEMENT MANUFACTURING METHOD
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Pub. No.: WO/2019/021903 International Application No.: PCT/JP2018/026886
Publication Date: 31.01.2019 International Filing Date: 18.07.2018
IPC:
H01L 21/301 (2006.01) ,B23K 26/53 (2014.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
[IPC code unknown for B23K 26/53]
Applicants:
浜松ホトニクス株式会社 HAMAMATSU PHOTONICS K.K. [JP/JP]; 静岡県浜松市東区市野町1126番地の1 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 4358558, JP
Inventors:
坂本 剛志 SAKAMOTO Takeshi; JP
杉浦 隆二 SUGIURA Ryuji; JP
近藤 裕太 KONDOH Yuta; JP
内山 直己 UCHIYAMA Naoki; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
黒木 義樹 KUROKI Yoshiki; JP
柴山 健一 SHIBAYAMA Kenichi; JP
Priority Data:
2017-14685928.07.2017JP
Title (EN) LAMINATED ELEMENT MANUFACTURING METHOD
(FR) PROCÉDÉ DE FABRICATION D'ÉLÉMENT STRATIFIÉ
(JA) 積層型素子の製造方法
Abstract:
(EN) A laminating step according to the present invention comprises: a first bonding step for bonding a circuit layer of a second wafer to a circuit layer of a first wafer; a polishing step for polishing a semiconductor substrate of the second wafer; and a second bonding step for bonding a circuit layer of a third wafer to the semiconductor substrate of the second wafer. In a laser-beam irradiation step, a modified region is formed by irradiation of the semiconductor substrate of the first wafer with a laser beam, and a crack is caused to extend, from the modified region, along the lamination direction of a laminated body.
(FR) L'invention concerne une étape de stratification comprenant : une première étape de liaison permettant de lier une couche de circuit d'une deuxième tranche à une couche de circuit d'une première tranche ; une étape de polissage permettant de polir un substrat semi-conducteur de la deuxième tranche ; et une deuxième étape de liaison permettant de lier une couche de circuit d'une troisième tranche au substrat semi-conducteur de la deuxième tranche. Dans une étape de rayonnement par faisceau laser, une zone modifiée est formée par l'exposition du substrat semi-conducteur de la première tranche à un faisceau laser, et une fissure est amenée à s'étendre, depuis la zone modifiée, le long de la direction de stratification d'un corps stratifié.
(JA) 積層工程は、第1ウェハの回路層に第2ウェハの回路層を接合する第1接合工程と、前記第2ウェハの半導体基板を研削する研削工程と、前記第2ウェハの前記半導体基板に前記第3ウェハの回路層を接合する第2接合工程と、を有する。レーザ光照射工程においては、前記第1ウェハの半導体基板に対してレーザ光を照射することにより改質領域を形成すると共に積層体の積層方向に沿って前記改質領域から亀裂を伸展させる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)