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1. (WO2019021852) SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
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Pub. No.: WO/2019/021852 International Application No.: PCT/JP2018/026427
Publication Date: 31.01.2019 International Filing Date: 13.07.2018
IPC:
H04N 5/357 (2011.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 21/822 (2006.01) ,H01L 23/522 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/146 (2006.01) ,H04N 5/369 (2011.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
357
Noise processing, e.g. detecting, correcting, reducing or removing noise
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
宮本 宗 MIYAMOTO Takashi; JP
秋山 義行 AKIYAMA Yoshiyuki; JP
角田 純一 TSUNODA Junichi; JP
児島 秀一 KOJIMA Shuuichi; JP
Agent:
西川 孝 NISHIKAWA Takashi; JP
稲本 義雄 INAMOTO Yoshio; JP
Priority Data:
2017-14536427.07.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET APPAREIL ÉLECTRONIQUE
(JA) 半導体装置および電子機器
Abstract:
(EN) The present technology relates to a semiconductor device and an electronic apparatus, whereby generation of noise in signals can be suppressed. This semiconductor device is provided with: a first semiconductor substrate wherein at least a part of a first conductor loop is formed; and a second semiconductor substrate that includes a first conductor layer and a second conductor layer, each having a conductor, said first conductor layer and second conductor layer forming a second conductor loop. The first conductor layer and the second conductor layer are configured such that the direction of a loop plane where a magnetic flux is generated from the second conductor loop, and the direction of a loop plane where the first conductor loop generates electromotive force are different from each other. The present technology can be applied to, for instance, CMOS image sensors.
(FR) La présente invention concerne un dispositif à semi-conducteur et un appareil électronique avec lesquels une génération de bruit dans des signaux peut être supprimée. Le dispositif à semi-conducteur comprend : un premier substrat semi-conducteur dans lequel au moins une partie d'une première boucle conductrice est formée ; et un second substrat semi-conducteur qui comprend une première couche conductrice et une seconde couche conductrice, chacune ayant un conducteur, ladite première couche conductrice et ladite seconde couche conductrice formant une seconde boucle conductrice. La première couche conductrice et la seconde couche conductrice sont configurées de telle sorte que la direction d'un plan de boucle où un flux magnétique est généré à partir de la seconde boucle conductrice et la direction d'un plan de boucle où la première boucle conductrice génère une force électromotrice sont différentes l'une de l'autre. La présente technologie peut être appliquée, par exemple, à des capteurs d’images CMOS.
(JA) 本技術は、信号におけるノイズの発生を抑制することができるようにする半導体装置および電子機器に関する。 半導体装置は、第1の導体ループの少なくとも一部が形成される第1の半導体基板と、第2の導体ループを形成する、導体を有する第1の導体層及び第2の導体層を含む第2の半導体基板とを備え、第1の導体層と第2の導体層は、第2の導体ループから磁束が発生するループ面の方向と、第1の導体ループに誘導起電力を発生させるループ面の方向と、が異なるように構成される。本技術は、例えば、CMOSイメージセンサに適用できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)