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1. (WO2019009877) PHASE CHANGE MEMORY STRUCTURES
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Pub. No.: WO/2019/009877 International Application No.: PCT/US2017/040558
Publication Date: 10.01.2019 International Filing Date: 01.07.2017
IPC:
H01L 45/00 (2006.01) ,H01L 27/24 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
MISHRA, Maneesh; US
BOHRA, Mihir H.; US
Agent:
OSBORNE, David W.; US
Priority Data:
Title (EN) PHASE CHANGE MEMORY STRUCTURES
(FR) STRUCTURES DE MÉMOIRE À CHANGEMENT DE PHASE
Abstract:
(EN) A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) above the phase change material layer. The dielectric material can have a top surface (135) that is higher than a top surface (125) of the top electrode layer. The bit line (140) can have a non-flat bottom surface that contacts the top surface of the dielectric material and protrudes down from the top surface of the dielectric material to a top surface of the memory cell.
(FR) La présente invention concerne une structure de mémoire à changement de phase (100) qui peut comprendre une cellule de mémoire, un matériau diélectrique (130) adjacent à la cellule de mémoire et une ligne de bits. La cellule de mémoire peut comprendre une couche de matériau à changement de phase (110) et une couche d'électrode supérieure (120) au-dessus de la couche de matériau à changement de phase. Le matériau diélectrique peut comporter une surface supérieure (135) qui est plus élevée qu'une surface supérieure (125) de la couche d'électrode supérieure. La ligne de bits (140) peut comporter une surface inférieure non plate qui entre en contact avec la surface supérieure du matériau diélectrique et fait saillie vers le bas à partir de la surface supérieure du matériau diélectrique jusqu'à une surface supérieure de la cellule de mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)