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1. (WO2019009873) DAMASCENE PATTERNING FOR THIN-FILM TRANSISTOR FABRICATION
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Pub. No.: WO/2019/009873 International Application No.: PCT/US2017/040552
Publication Date: 10.01.2019 International Filing Date: 01.07.2017
IPC:
H01L 29/786 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
LIN, Kevin [US/US]; US
LE, Van [US/US]; US
KAVALIEROS, Jack [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 94054, US
Inventors:
LIN, Kevin; US
LE, Van; US
KAVALIEROS, Jack; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) DAMASCENE PATTERNING FOR THIN-FILM TRANSISTOR FABRICATION
(FR) FORMATION DE MOTIFS DE DAMASQUINAGE POUR LA FABRICATION DE TRANSISTORS À COUCHES MINCES
Abstract:
(EN) Embodiments of the invention include thin-film transistors and methods of making such devices with damascene processes. In an embodiment the thin-film transistor (TFT) device includes an interlayer dielectric (ILD) layer, where a trench is formed into the ILD layer. In an embodiment a TFT semiconductor layer formed in the trench, wherein extensions of the TFT semiconductor layer extend up sidewalls of the trench. In an embodiment, a capping layer formed over a top surface of the TFT semiconductor layer. Additional embodiments may include a source electrode and a drain electrode, where the source electrode and the drain electrode contact a surface of the TFT semiconductor layer, and a gate electrode separated from a surface of the TFT semiconductor layer by a gate dielectric layer.
(FR) Des modes de réalisation de la présente invention comprennent des transistors à couches minces et des procédés de formation de tels dispositifs avec des procédés de damasquinage. Dans un mode de réalisation, le dispositif de transistor à couches minces (TFT) comprend une couche diélectrique intercouche (ILD), une tranchée étant formée dans la couche ILD. Dans un mode de réalisation, une couche semi-conductrice TFT est formée dans la tranchée, des extensions de la couche semi-conductrice TFT s'étendant jusqu'à des parois latérales de la tranchée. Dans un mode de réalisation, une couche de transition est formée sur une surface supérieure de la couche semi-conductrice TFT. Des modes de réalisation supplémentaires peuvent comprendre une électrode de source et une électrode de drain, l'électrode de source et l'électrode de drain étant en contact avec une surface de la couche semi-conductrice TFT, et une électrode de grille séparée d'une surface de la couche semi-conductrice TFT par une couche diélectrique de grille.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)