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1. (WO2019009872) SELF-ALIGNED BACK-GATE TOP-CONTACT THIN-FILM TRANSISTOR
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Pub. No.: WO/2019/009872 International Application No.: PCT/US2017/040551
Publication Date: 10.01.2019 International Filing Date: 01.07.2017
IPC:
H01L 29/786 (2006.01) ,H01L 29/40 (2006.01) ,H01L 21/033 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
033
comprising inorganic layers
Applicants:
LIN, Kevin [US/US]; US
LE, Van [US/US]; US
SHARMA, Abhishek [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 94054, US
Inventors:
LIN, Kevin; US
LE, Van; US
SHARMA, Abhishek; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) SELF-ALIGNED BACK-GATE TOP-CONTACT THIN-FILM TRANSISTOR
(FR) TRANSISTOR EN COUCHES MINCES AUTO-ALIGNÉ À CONTACT SUPÉRIEUR ET À GRILLE ARRIÈRE
Abstract:
(EN) Embodiments of the invention include a method of forming a thin-film transistor (TFT) with self-aligned source and drain electrodes. In an embodiment, the method includes forming a TFT stack. Embodiments include forming a first backbone hardmask over the TFT stack, and forming spacers along sidewalls of the first backbone hardmask. In an embodiment the method also includes forming first trenches into the TFT stack, where the first backbone hardmask and the spacers are used as an etch mask to define the trenches, and depositing a interlayer dielectric (ILD) into the trenches and forming a second backbone hardmask over the ILD, where the second backbone hardmask is formed between the spacers, and removing the spacers. In an embodiment the method includes forming second trenches into the material stack, and forming source electrodes and drain electrodes in the trenches.
(FR) Selon des modes de réalisation, la présente invention porte sur un procédé de formation d'un transistor en couches minces (TFT) doté d'électrodes de source et de drain auto-alignées. Dans un mode de réalisation, le procédé consiste à former un empilement de TFT. Des modes de réalisation consistent à former un premier masque dur de squelette sur l'empilement de TFT, et à former des éléments de cloisonnement le long de parois latérales du premier masque dur de squelette. Dans un mode de réalisation, le procédé consiste également à former des premières tranchées dans l'empilement de TFT, le premier masque dur de squelette et les éléments de cloisonnement étant utilisés comme masque de gravure pour délimiter les tranchées, à déposer un diélectrique de couche intermédiaire (ILD) dans les tranchées et à former un second masque dur de squelette sur l'ILD, le second masque dur de squelette étant formé entre les éléments de cloisonnement, et à retirer les éléments de cloisonnement. Dans un mode de réalisation, le procédé consiste à former des secondes tranchées dans l'empilement de matériaux, et à former des électrodes de source et des électrodes de drain dans les tranchées.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)